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Rolf Drechsler
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- affiliation: University of Bremen, Institute of Computer Science
- affiliation: German Research Centre for Artificial Intelligence (DFKI), Bremen
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2020 – today
- 2024
- [j155]Alireza Mahzoon, Rolf Drechsler:
Polynomial Formal Verification of Arithmetic Circuits. Found. Trends Electron. Des. Autom. 14(3): 171-244 (2024) - [j154]Chandan Kumar Jha, Muhammad Hassan, Rolf Drechsler:
cecApprox: Enabling Automated Combinational Equivalence Checking for Approximate Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 71(7): 3282-3293 (2024) - [j153]Chandan Kumar Jha, Khushboo Qayyum, Kemal Çaglar Coskun, Simranjeet Singh, Muhammad Hassan, Rainer Leupers, Farhad Merchant, Rolf Drechsler:
veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing. IEEE Trans. Circuits Syst. I Regul. Pap. 71(9): 4169-4179 (2024) - [j152]Mehran Goli, Rolf Drechsler:
Early SoCs Information Flow Policies Validation Using SystemC-Based Virtual Prototypes at the ESL. ACM Trans. Embed. Comput. Syst. 23(5): 67:1-67:20 (2024) - [j151]Kousik Bhunia, Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler:
ReSG: A Data Structure for Verification of Majority-based In-memory Computing on ReRAM Crossbars. ACM Trans. Embed. Comput. Syst. 23(6): 90:1-90:24 (2024) - [c741]Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant:
MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory. ASPDAC 2024: 282-287 - [c740]Ece Nur Demirhan Coskun, Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler:
Security Coverage Metrics for Information Flow at the System Level. ASPDAC 2024: 945-950 - [c739]Christina Plump, Daniel Christopher Hoinkiss, Jörn Huber, Bernhard J. Berger, Matthias Günther, Christoph Lüth, Rolf Drechsler:
Finding the perfect MRI sequence for your patient - Towards an optimisation workflow for MRI-sequences. CEC 2024: 1-9 - [c738]Kemal Çaglar Coskun, Muhammad Hassan, Lars Hedrich, Rolf Drechsler:
Efficient Equivalence Checking of Nonlinear Analog Circuits using Gradient Ascent. DAC 2024: 51:1-51:6 - [c737]Khushboo Qayyum, Muhammad Hassan, Sallar Ahmadi-Pour, Chandan Kumar Jha, Rolf Drechsler:
Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware Verification. DAC 2024: 349:1-349:2 - [c736]Muhammad Hassan, Sallar Ahmadi-Pour, Khushboo Qayyum, Chandan Kumar Jha, Rolf Drechsler:
LLM-Guided Formal Verification Coupled with Mutation Testing. DATE 2024: 1-2 - [c735]Caroline Dominik, Rolf Drechsler:
Polynomial Formal Verification of Sequential Circuits. DATE 2024: 1-6 - [c734]Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler:
Dynamic Realization of Multiple Control Toffoli Gate. DATE 2024: 1-6 - [c733]Sajjad Parvin, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler:
Hidden Cost of Circuit Design with RFETs. DATE 2024: 1-2 - [c732]Lennart Weingarten, Kamalika Datta, Abhoy Kole, Rolf Drechsler:
Complete and Efficient Verification for a RISC-V Processor Using Formal Verification. DATE 2024: 1-6 - [c731]Jan Zielasko, Rune Krauss, Marcel Merten, Rolf Drechsler:
Improving Virtual Prototype Driven Hardware Optimization by Merging Instruction Sequences. DDECS 2024: 73-78 - [c730]Payam Habiby, Fatemeh Shirinzadeh, Sebastian Huhn, Rolf Drechsler:
A Multi-Objective Evolutionary Approach for Test Network Design. ETS 2024: 1-4 - [c729]Mohamed A. Nadeem, Chandan Kumar Jha, Rolf Drechsler:
Polynomial Formal Verification of Approximate Adders with Constant Cutwidth. ETS 2024: 1-6 - [c728]Bernhard Johannes Berger, Christina Plump, Lauren Paul, Rolf Drechsler:
EvoAl - Codeless Domain-Optimisation. GECCO Companion 2024: 1640-1648 - [c727]Helen Pfuhl, Lena Steinmann, Dirk Nowotka, Rolf Drechsler:
Aufbau einer überregionalen Data-Science-Community. INFORMATIK 2024: 2197-2203 - [c726]Khushboo Qayyum, Abhoy Kole, Kamalika Datta, Muhammad Hassan, Rolf Drechsler:
Exploring the Potential of Decision Diagrams for Efficient In-Memory Design Verification. ACM Great Lakes Symposium on VLSI 2024: 502-506 - [c725]Mohamed A. Nadeem, Rolf Drechsler:
Polynomial Formal Verification of Multi-Valued Logic Circuits within Constant Cutwidth Architectures. ISMVL 2024: 149-154 - [c724]Abhoy Kole, Kamalika Datta, Rolf Drechsler:
Design Automation Challenges and Benefits of Dynamic Quantum Circuit in Present NISQ Era and Beyond: (Invited Paper). ISVLSI 2024: 601-606 - [c723]Ruidi Qiu, Grace Li Zhang, Rolf Drechsler, Ulf Schlichtmann, Bing Li:
AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design. MLCAD 2024: 18:1-18:10 - [c722]Liam Hurwitz, Kamalika Datta, Abhoy Kole, Rolf Drechsler:
Is Simulation the only Alternative for Effective Verification of Dynamic Quantum Circuits? RC 2024: 201-217 - [c721]Sneha Lahiri, Megha Kesh, Rupsa Mandal, Anirban Bhattacharjee, Sovan Bhattacharya, Dola Sinha, Chandan Bandyopadhyay, Laxmidhar Biswal, Robert Wille, Rolf Drechsler:
A Dynamic Programming Based Graph Traversal Approach for Efficient Implementation of Nearest Neighbor Architecture in 2D. VLSID 2024: 306-311 - [c720]Fatemeh Shirinzadeh, Arighna Deb, Saeideh Shirinzadeh, Abhoy Kole, Kamalika Datta, Rolf Drechsler:
In-Memory SAT-Solver for Self-Verification of Programmable Memristive Architectures. VLSID 2024: 384-389 - [c719]Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin B. Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana:
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array. VLSID 2024: 565-570 - [c718]Chandan Kumar Jha, Sallar Ahmadi-Pour, Rolf Drechsler:
Input Distribution Aware Library of Approximate Adders Based on Memristor-Aided Logic. VLSID 2024: 577-582 - [i30]Sören Tempel, Tobias Brandt, Christoph Lüth, Rolf Drechsler:
BinSym: Binary-Level Symbolic Execution using Formal Descriptions of Instruction Semantics. CoRR abs/2404.04132 (2024) - [i29]Simranjeet Singh, Ankit Bende, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Sachin B. Patkar, Farhad Merchant:
In-Memory Mirroring: Cloning Without Reading. CoRR abs/2407.02921 (2024) - [i28]Ruidi Qiu, Grace Li Zhang, Rolf Drechsler, Ulf Schlichtmann, Bing Li:
AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design. CoRR abs/2407.03891 (2024) - [i27]Bernhard J. Berger, Christina Plump, Rolf Drechsler:
EvoAl2048. CoRR abs/2408.16780 (2024) - [i26]Abhoy Kole, Mohammed E. Djeridane, Lennart Weingarten, Kamalika Datta, Rolf Drechsler:
qSAT: Design of an Efficient Quantum Satisfiability Solver for Hardware Equivalence Checking. CoRR abs/2409.03917 (2024) - 2023
- [j150]Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Phrangboklang Lyngton Thangkhiew, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant:
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style. IEEE Embed. Syst. Lett. 15(4): 230-233 (2023) - [j149]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Specification-Based Symbolic Execution for Stateful Network Protocol Implementations in IoT. IEEE Internet Things J. 10(11): 9544-9555 (2023) - [j148]Kamalika Datta, Arighna Deb, Abhoy Kole, Rolf Drechsler:
Impact of sneak paths on in-memory logic design in memristive crossbars. it Inf. Technol. 65(1-2): 29-39 (2023) - [j147]Chandan Kumar Jha, Sallar Ahmadi-Pour, Rolf Drechsler:
MARADIV: Library of MAGIC-Based Approximate Restoring Array Divider Benchmark Circuits for In-Memory Computing Using Memristors. IEEE Trans. Circuits Syst. II Express Briefs 70(7): 2635-2639 (2023) - [c717]Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler:
Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM Crossbars. ASP-DAC 2023: 19-25 - [c716]Rune Krauss, Mehran Goli, Rolf Drechsler:
EDDY: A Multi-Core BDD Package with Dynamic Memory Management and Reduced Fragmentation. ASP-DAC 2023: 423-428 - [c715]Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler:
Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - A RISC-V Case Study. ASP-DAC 2023: 683-689 - [c714]Alireza Mahzoon, Rolf Drechsler:
Polynomial Formal Verification of Complex Circuits Using a Hybrid Proof Engine. Applicable Formal Methods for Safe Industrial Products 2023: 308-319 - [c713]Bernhard J. Berger, Christina Plump, Rolf Drechsler:
EVOAL: A Domain-Specific Language-Based Approach to Optimisation. CEC 2023: 1-10 - [c712]Sajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler:
Lo-RISK: Design of a Low Optical Leakage and High Performance RISC-V Core. COINS 2023: 1-4 - [c711]Niklas Bruns, Vladimir Herdt, Rolf Drechsler:
Processor Verification using Symbolic Execution: A RISC-V Case-Study. DATE 2023: 1-6 - [c710]Kemal Çaglar Coskun, Muhammad Hassan, Rolf Drechsler:
Equivalence Checking of System-Level and SPICE-Level Models of Static Nonlinear Circuits. DATE 2023: 1-6 - [c709]Rolf Drechsler, Alireza Mahzoon:
Divide and Verify: Using a Divide-and-Conquer Strategy for Polynomial Formal Verification of Complex Circuits. DATE 2023: 1-2 - [c708]Jan Kleinekathöfer, Alireza Mahzoon, Rolf Drechsler:
Polynomial Formal Verification of Floating Point Adders. DATE 2023: 1-2 - [c707]Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler:
Extending the Design Space of Dynamic Quantum Circuits for Toffoli based Network. DATE 2023: 1-6 - [c706]Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler:
FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing. DATE 2023: 1-2 - [c705]Jens Trommer, Niladri Bhattacharjee, Thomas Mikolajick, Sebastian Huhn, Marcel Merten, Mohammed E. Djeridane, Muhammad Hassan, Rolf Drechsler, Shubham Rai, Nima Kavand, Armin Darjani, Akash Kumar, V. Sessi, M. Drescher, S. Kolodinski, M. Wiatr:
Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors. DATE 2023: 1-6 - [c704]Rune Krauss, Mehran Goli, Rolf Drechsler:
Efficient Binary Decision Diagram Manipulation by Reducing the Number of Intermediate Nodes. DDECS 2023: 73-78 - [c703]Marcel Merten, Muhammad Hassan, Rolf Drechsler:
Quality Assessment of Logic Locking Mechanisms using Pseudo-Boolean Optimization Techniques. DDECS 2023: 105-110 - [c702]Payam Habiby, Sebastian Huhn, Rolf Drechsler:
RC-IJTAG: A Methodology for Designing Remotely-Controlled IEEE 1687 Scan Networks. DFT 2023: 1-6 - [c701]Weiyan Zhang, Mehran Goli, Muhammad Hassan, Rolf Drechsler:
Efficient ML-Based Performance Estimation Approach Across Different Microarchitectures for RISC-V Processors. DSD 2023: 693-699 - [c700]Payam Habiby, Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich, Sebastian Huhn, Rolf Drechsler:
Synthesis of IJTAG Networks for Multi-Power Domain Systems on Chips. ETS 2023: 1-6 - [c699]Marcel Merten, Sebastian Huhn, Rolf Drechsler:
Increasing SAT-Resilience of Logic Locking Mechanisms using Formal Methods. ETS 2023: 1-6 - [c698]Milan Funck, Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler:
Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification. FDL 2023: 1-8 - [c697]Christopher A. Metz, Christina Plump, Bernhard J. Berger, Rolf Drechsler:
Hybrid PTX Analysis for GPU accelerated CNN inferencing aiding Computer Architecture Design. FDL 2023: 1-8 - [c696]Sören Tempel, Tobias Brandt, Christoph Lüth, Rolf Drechsler:
Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models. FDL 2023: 1-8 - [c695]Jan Zielasko, Rolf Drechsler:
Virtual Prototype Driven Application Specific Hardware Optimization. FDL 2023: 1-8 - [c694]Marcel Merten, Rune Krauss, Rolf Drechsler:
Scalable Neuroevolution of Ensemble Learners. GECCO Companion 2023: 667-670 - [c693]Christina Plump, Bernhard J. Berger, Rolf Drechsler:
Repetitive Processes and Their Surrogate-Model Congruent Encoding for Evolutionary Algorithms - A Theoretic Proposal. GECCO Companion 2023: 2289-2296 - [c692]Lena Steinmann, Dirk Nowotka, Lea Oberländer, Helen Pfuhl, Heiner Stuckenschmidt, Rolf Drechsler:
Workshop: "Aktuelle Entwicklungen und Perspektiven (an Hochschulen) im Bereich Data Science". GI-Jahrestagung 2023: 73-80 - [c691]Tim Meywerk, Vladimir Herdt, Rolf Drechsler:
Coverage-Guided Fuzzing for Plan-Based Robotics. ICAART (2) 2023: 106-114 - [c690]Christopher A. Metz, Mehran Goli, Rolf Drechsler:
Fast and Accurate: Machine Learning Techniques for Performance Estimation of CNNs for GPGPUs. IPDPS Workshops 2023: 754-760 - [c689]Rolf Drechsler, Alireza Mahzoon:
Towards Polynomial Formal Verification of AI-Generated Arithmetic Circuits. ISDCS 2023: 1-4 - [c688]Rolf Drechsler, Martha Schnieber:
Automated Polynomial Formal Verification: Human-Readable Proof Generation. iSES 2023: 1-3 - [c687]Kamalika Datta, Rolf Drechsler:
Memristors: Device Modeling, Design and Verification. iSES 2023: 254-259 - [c686]Ece Nur Demirhan Coskun, Muhammad Hassan, Mehran Goli, Rolf Drechsler:
VAST: Validation of VP-based Heterogeneous Systems against Availability Security Properties using Static Information Flow Tracking. ISQED 2023: 1-8 - [c685]Lennart Weingarten, Alireza Mahzoon, Mehran Goli, Rolf Drechsler:
Polynomial Formal Verification of a Processor: A RISC-V Case Study. ISQED 2023: 1-7 - [c684]Sajjad Parvin, Mehran Goli, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler:
LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical Probing. ISVLSI 2023: 1-6 - [c683]Sana Hassan Imam, Christopher A. Metz, Lars Hornuf, Rolf Drechsler:
Classifying Crowdsouring Platform Users' Engagement Behaviour using Machine Learning and XAI. MuC (Workshopband) 2023 - [c682]Martha Schnieber, Rolf Drechsler:
Polynomial Formal Verification of KFDD Circuits. MEMOCODE 2023: 82-89 - [c681]Rolf Drechsler, Martha Schnieber:
Next-Generation Automatic Human-Readable Proofs Enabling Polynomial Formal Verification. MEMOCODE 2023: 122-125 - [c680]Lennart Weingarten, Kamalika Datta, Rolf Drechsler:
PolyMiR: Polynomial Formal Verification of the MicroRV32 Processor. NANOARCH 2023: 24:1-24:6 - [c679]Kamalika Datta, Arighna Deb, Fatemeh Shirinzadeh, Abhoy Kole, Saeideh Shirinzadeh, Rolf Drechsler:
Verification of In-Memory Logic Design using ReRAM Crossbars. NEWCAS 2023: 1-5 - [c678]Chandan Kumar Jha, Rolf Drechsler:
Benchmarking Multiplier Architectures for MAGIC Based In-Memory Computing. NEWCAS 2023: 1-5 - [c677]Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Rishad A. Shafik, Alex Yakovlev, Sachin B. Patkar, Farhad Merchant:
Finite State Automata Design using 1T1R ReRAM Crossbar. NEWCAS 2023: 1-5 - [c676]Kamalika Datta, Abhoy Kole, Indranil Sengupta, Rolf Drechsler:
Improved Cost-Metric for Nearest Neighbor Mapping of Quantum Circuits to 2-Dimensional Hexagonal Architecture. RC 2023: 218-231 - [c675]Abhoy Kole, Kamalika Datta, Philipp Niemann, Indranil Sengupta, Rolf Drechsler:
Exploiting the Benefits of Clean Ancilla Based Toffoli Gate Decomposition Across Architectures. RC 2023: 232-244 - [c674]Mohamed A. Nadeem, Jan Kleinekathöfer, Rolf Drechsler:
Polynomial Formal Verification exploiting Constant Cutwidth. RSP 2023: 03:1-03:7 - [d3]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Artifacts for the IEEE Internet of Things Journal Publication: Specification-based Symbolic Execution for Stateful Network Protocol Implementations in the IoT. Zenodo, 2023 - [i25]Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Rishad A. Shafik, Alex Yakovlev, Sachin B. Patkar, Farhad Merchant:
Finite State Automata Design using 1T1R ReRAM Crossbar. CoRR abs/2304.13552 (2023) - [i24]Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Phrangboklang Lyngton Thangkhiew, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant:
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style. CoRR abs/2307.03669 (2023) - [i23]Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant:
MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory. CoRR abs/2309.04868 (2023) - [i22]Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin B. Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana:
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array. CoRR abs/2310.10460 (2023) - [i21]Sallar Ahmadi-Pour, Pascal Pieper, Rolf Drechsler:
Virtual-Peripheral-in-the-Loop : A Hardware-in-the-Loop Strategy to Bridge the VP/RTL Design-Gap. CoRR abs/2311.00442 (2023) - 2022
- [j146]Vladimir Herdt, Rolf Drechsler:
Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges. Sci. China Inf. Sci. 65(1) (2022) - [j145]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Towards Quantification and Visualization of the Effects of Concretization During Concolic Testing. IEEE Embed. Syst. Lett. 14(4): 195-198 (2022) - [j144]Dev Narayan Yadav, Phrangboklang Lyngton Thangkhiew, Kamalika Datta, Sandip Chakraborty, Rolf Drechsler, Indranil Sengupta:
FAMCroNA: Fault Analysis in Memristive Crossbars for Neuromorphic Applications. J. Electron. Test. 38(2): 145-163 (2022) - [j143]Saman Fröhlich, Rolf Drechsler:
Unlocking approximation for in-memory computing with Cartesian genetic programming and computer algebra for arithmetic circuits. it Inf. Technol. 64(3): 99-107 (2022) - [j142]Robert Wille, Rolf Drechsler:
Introduction to the Special Issue on Design Automation for Quantum Computing. ACM J. Emerg. Technol. Comput. Syst. 18(1): 10:1-10:2 (2022) - [j141]Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler:
Parallel Computing of Graph-based Functions in ReRAM. ACM J. Emerg. Technol. Comput. Syst. 18(2): 41:1-41:24 (2022) - [j140]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
SymEx-VP: An open source virtual prototype for OS-agnostic concolic testing of IoT firmware. J. Syst. Archit. 126: 102456 (2022) - [j139]F. Lalchhandama, Kamalika Datta, Sandip Chakraborty, Rolf Drechsler, Indranil Sengupta:
CoMIC: Complementary Memristor based in-memory computing in 3D architecture. J. Syst. Archit. 126: 102480 (2022) - [j138]Dev Narayan Yadav, Phrangboklang Lyngton Thangkhiew, Kamalika Datta, Sandip Chakraborty, Rolf Drechsler, Indranil Sengupta:
Feed-Forward learning algorithm for resistive memories. J. Syst. Archit. 131: 102730 (2022) - [j137]Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler:
The MicroRV32 framework: An accessible and configurable open source RISC-V cross-level platform for education and research. J. Syst. Archit. 133: 102757 (2022) - [j136]Philipp Niemann, Alexandre A. A. de Almeida, Gerhard W. Dueck, Rolf Drechsler:
Template-based mapping of reversible circuits to IBM quantum computers. Microprocess. Microsystems 90: 104487 (2022) - [j135]Mehran Goli, Rolf Drechsler:
Through the Looking Glass: Automated Design Understanding of SystemC-Based VPs at the ESL. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 1181-1185 (2022) - [j134]Alireza Mahzoon, Daniel Große, Rolf Drechsler:
RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1573-1586 (2022) - [c673]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Automated Detection of Spatial Memory Safety Violations for Constrained Devices. ASP-DAC 2022: 160-165 - [c672]Sajjad Parvin, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler:
Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design Techniques. ASP-DAC 2022: 429-435 - [c671]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification. ATVA 2022: 77-82 - [c670]Christina Plump, Bernhard J. Berger, Rolf Drechsler:
Using density of training data to improve evolutionary algorithms with approximative fitness functions. CEC 2022: 1-10 - [c669]Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Verifying SystemC TLM peripherals using modern C++ symbolic execution tools. DAC 2022: 1177-1182 - [c668]Alireza Mahzoon, Daniel Große, Christoph Scholl, Alexander Konrad, Rolf Drechsler:
Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability. DAC 2022: 1183-1188 - [c667]Wolfgang Ecker, Peer Adelt, Wolfgang Müller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, Gerhard Angst, Ralf Wimmer, Andreas Mauderer, Rafael Stahl, Karsten Emrich, Daniel Mueller-Gritschneder, Bernd Becker, Philipp Scholl, Eyck Jentzsch, Jan Schlamelcher, Kim Grüttner, Paul Palomero Bernardo, Oliver Bringmann, Mihaela Damian, Julian Oppermann, Andreas Koch, Jörg Bormann, Johannes Partzsch, Christian Mayr, Wolfgang Kunz:
The Scale4Edge RISC-V Ecosystem. DATE 2022: 808-813 - [c666]Niklas Bruns, Vladimir Herdt, Eyck Jentzsch, Rolf Drechsler:
Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging. DATE 2022: 1123-1126 - [c665]Saman Fröhlich, Rolf Drechsler:
LiM-HDL: HDL-Based Synthesis for In-Memory Computing. DATE 2022: 1395-1400 - [c664]Rolf Drechsler, Alireza Mahzoon, Mehran Goli:
Towards Polynomial Formal Verification of Complex Arithmetic Circuits. DDECS 2022: 1-6 - [c663]Milan Funck, Vladimir Herdt, Rolf Drechsler:
Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions. DDECS 2022: 14-19 - [c662]Weiyan Zhang, Mehran Goli, Rolf Drechsler:
Early Performance Estimation of Embedded Software on RISC-V Processor using Linear Regression. DDECS 2022: 20-25 - [c661]Kemal Çaglar Coskun, Muhammad Hassan, Rolf Drechsler:
Equivalence Checking of System-Level and SPICE-Level Models of Linear Analog Filters. DDECS 2022: 160-165 - [c660]