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Shanq-Jang Ruan
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Publications
- 2006
- [c20]Kun-Lin Tsai, Ju-Yueh Lee, Shanq-Jang Ruan, Feipei Lai:
Low power scheduling method using multiple supply voltages. ISCAS 2006 - 2005
- [j4]Shanq-Jang Ruan, Kun-Lin Tsai, Edwin Naroska, Feipei Lai:
Bipartitioning and encoding in low-power pipelined circuits. ACM Trans. Design Autom. Electr. Syst. 10(1): 24-32 (2005) - [c14]Kun-Lin Tsai, Szu-Wei Chaung, Feipei Lai, Shanq-Jang Ruan:
A low power scheduling method using dual Vdd and dual Vth. ISCAS (1) 2005: 684-687 - 2003
- [j3]Yen-Jen Chang, Shanq-Jang Ruan, Feipei Lai:
Design and analysis of low-power cache using two-level filter scheme. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 568-580 (2003) - [c12]Kun-Lin Tsai, Feipei Lai, Shanq-Jang Ruan, Szu-Wei Chaung:
State Reordering for Low Power Combinational Logic. Asia-Pacific Computer Systems Architecture Conference 2003: 268-276 - [c11]Edwin Naroska, Shanq-Jang Ruan, Chia-Lin Ho, Said Mchaalia, Feipei Lai, Uwe Schwiegelshohn:
A novel approach for digital waveform compression. ASP-DAC 2003: 712-715 - [c10]Edwin Naroska, Shanq-Jang Ruan, Feipei Lai, Uwe Schwiegelshohn, Le-Chin Liu:
On optimizing power and crosstalk for bus coupling capacitance using genetic algorithms. ISCAS (5) 2003: 277-280 - 2002
- [j2]Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Feipei Lai, Uwe Schwiegelshohn:
ENPCO: an entropy-based partition-codec algorithm to reduce power for bipartition-codec architecture in pipelined circuits. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 942-949 (2002) - [c9]Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Chia-Lin Ho, Feipei Lai:
Energy analysis of bipartition architecture for pipelined circuits. APCCAS (2) 2002: 7-11 - [c8]Shanq-Jang Ruan, Edwin Naroska, Chia-Lin Ho, Feipei Lai:
Power Analysis of Bipartition and Dual-Encoding Architecture for Pipelined Circuits. ICCD 2002: 327- - [c7]Yen-Jen Chang, Feipei Lai, Shanq-Jang Ruan:
Cache Design for Eliminating the Address Translation Bottleneck and Reducing the Tag Area Cost. ICCD 2002: 334-339 - [c6]Yen-Jen Chang, Feipei Lai, Shanq-Jang Ruan:
An Efficient Two-Level Filter Scheme for Low Power Cache. IWLS 2002: 61-66 - 2001
- [j1]Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Kun-Lin Tsai:
A bipartition-codec architecture to reduce power in pipelinedcircuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2): 343-348 (2001) - [c5]Po-Hung Chen, Shanq-Jang Ruan, Kuen-Pin Wu, Dai-Xun Hu, Feipei Lai, Kun-Lin Tsai:
An entropy-based algorithm to reduce area overhead for bipartition-codec architecture. ISCAS (5) 2001: 49-52 - [c4]Shanq-Jang Ruan, Jen-Chiun Lin, Po-Hung Chen, Kun-Lin Tsai, Feipei Lai:
Synthesis of partition-codec architecture for low power and small area circuit design. ISCAS (5) 2001: 523-526 - 2000
- [c3]Shanq-Jang Ruan, Jen-Chiun Lin, Po-Hung Chen, Feipei Lai, Kun-Lin Tsai, Chung-Wei Yu:
An effective output-oriented algorithm for low power multipartition architecture. ICECS 2000: 609-612 - [c2]Kuen-Pin Wu, Shanq-Jang Ruan, Feipei Lai, Chih-Kuang Tseng:
On Key Distribution in Secure Multicasting. LCN 2000: 208-212 - 1999
- [c1]Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Shyh-Jong Chen, Xian-Jun Huang:
A bipartition-codec architecture to reduce power in pipelined circuits. ICCAD 1999: 84-90
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