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ORCIDASP-DAC 2003: Bangalore, India
- Hiroto Yasuura:
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003. ACM 2003, ISBN 0-7803-7660-9
Bus encoding and memory optimization
- Yazdan Aghaghiri, Farzan Fallah, Massoud Pedram:
BEAM: bus encoding based on instruction-set-aware memories. 3-8 - Satoshi Komatsu, Masahiro Fujita:
Irredundant address bus encoding techniques based on adaptive codebooks for low power. 9-14 - Sri Parameswaran
, Jörg Henkel, Haris Lekatsas:
Multi-parametric improvements for embedded systems using code-placement and address bus coding. 15-21 - Junghee Lee, Chanik Park, Soonhoi Ha:
Memory access pattern analysis and stream cache design for multimedia applications. 22-27
DSM interconnect and gate issues
- Kenichi Okada, Kento Yamaoka, Hidetoshi Onodera:
A statistical gate delay model for intra-chip and inter-chip variabilities. 31-36 - Muzhou Shao, D. F. Wong, Youxin Gao, Huijing Cao, Li-Pen Yuan:
A fast and accurate method for interconnect current calculation. 37-42 - Soroush Abbaspour, Massoud Pedram:
Calculating the effective capacitance for the RC interconnect in VDSM technologies. 43-48 - Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura:
Reduction of crosstalk noise by optimizing 3-D configuration of the routing grid. 49-52 - Shamik Das, Anantha P. Chandrakasan, Rafael Reif:
Design tools for 3-D integrated circuits. 53-56
Embedded software: task scheduling and compilation
- Jennifer L. Wong, Gang Qu, Miodrag Potkonjak:
An on-line approach for power minimization in QoS sensitive systems. 59-64 - Yumin Zhang, Xiaobo Sharon Hu, Danny Z. Chen:
Energy minimization of real-time tasks on variable voltage processors with transition energy overhead. 65-70 - Zhong Wang, Xiaobo Sharon Hu, Edwin Hsing-Mean Sha:
Register aware scheduling for distributed cache clustered architecture. 71-76 - Manish Verma, Stefan Steinke, Peter Marwedel:
Data partitioning for maximal scratchpad usage. 77-83
Combinational and sequential verification
- Maher N. Mneimneh, Karem A. Sakallah:
SAT-based sequential depth computation. 87-92 - Andreas G. Veneris, Alexander Smith, Magdy S. Abadir:
Logic verification based on diagnosis techniques. 93-98 - Yirng-An Chen, Fang-Sung Chen:
Algorithms for compacting error traces. 99-103 - Jian Liu, Eugene Shragowitz:
Transaction-based waveform analysis for IP selection. 104-107 - Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
An automatic interconnection rectification technique for SoC design integration. 108-111
C-based specification and ASIP design
- Frederic Doucet, Sandeep K. Shukla, Rajesh K. Gupta:
Typing abstractions and management in a component framework. 115-122 - Farzan Fallah, Indradeep Ghosh, Masahiro Fujita:
Event-driven observability enhanced coverage analysis of C programs for functional validation. 123-128 - Jun Kyoung Kim, Tag Gon Kim:
Trace-driven rapid pipeline architecture evaluation scheme for ASIP design. 129-134 - Koichi Tachikake, Nozomu Togawa, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki:
A hardware/software partitioning algorithm for SIMD processor cores. 135-140
On-chip inductance
- Atsushi Kurokawa, Takashi Sato, Hiroo Masuda:
Approximate formulae approach for efficient inductance extraction. 143-148 - Takashi Sato, Toshiki Kanamoto, Atsushi Kurokawa, Yoshiyuki Kawakami, Hiroki Oka, Tomoyasu Kitaura, Hiroyuki Kobayashi, Masanori Hashimoto:
Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF. 149-155 - Guoan Zhong, Cheng-Kok Koh, Kaushik Roy:
A metric for analyzing effective on-chip inductive coupling. 156-161 - Jun Chen, Lei He:
Determination of worst-case crosstalk noise for non-switching victims in GHz+ interconnects. 162-167
Circuit and modeling
- Albert Z. Wang:
Recent developments in ESD protection for RF ICs. 171-178 - Kazuya Hisamitsu, Hiroaki Ueno, Masayasu Tanaka, Daisuke Kitamaru, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama:
Temperature-independence-point properties for 0.1μm-scale pocket-implant technologies and the impact on circuit design. 179-183 - Yuichi Tanji, Masaya Suzuki, Takayuki Watanabe, Hideki Asai:
Behavioral modeling of EM devices by selective orthogonal matrix least-squares method. 184-188
Logic optimization and technology mapping
- Tomas Bengtsson, Andrés Martinelli, Elena Dubrova:
A BDD-based fast heuristic algorithm for disjoint decomposition. 191-196 - Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya:
Logic optimization for asynchronous speed independent controllers using transduction method. 197-202 - Chang Woo Kang, Massoud Pedram:
Technology mapping for low leakage power and high speed with hot-carrier effect consideration. 203-208 - Debasis Samanta, M. C. Dharmadeep, Ajit Pal:
Synthesis of high performance low power PTL circuits. 209-212 - Chi-Chou Kao, Yen-Tai Lai:
A technology mapping algorithm for heterogeneous FPGAs. 213-216
SoC and NoC
- Mohamed-Anouar Dziri, Firaz Samet, Flávio Rech Wagner, Wander O. Cesário, Ahmed Amine Jerraya:
Combining architecture exploration and a path to implementation to build a complete SoC design flow from system specification to RTL. 219-224 - Tudor Dumitras, Sam Kerner, Radu Marculescu:
Towards on-chip fault-tolerant communication. 225-232 - Jingcao Hu, Radu Marculescu:
Energy-aware mapping for tile-based NoC architectures under performance constraints. 233-239
Clock synthesis and capacitance extraction
- Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili:
Adaptive wire adjustment for bounded skew Clock Distribution Network. 243-248 - Qi Wang, Sumit Roy:
Power minimization by clock root gating. 249-254 - Taotao Lu, Zeyi Wang, Xianlong Hong:
BBE: hierarchical computation of 3-D interconnect capacitance with BEM block extraction. 255-260 - Shu Yan, Jianguo Liu, Weiping Shi:
Improving boundary element methods for parasitic extraction. 261-267
Analysis methodologies for circuits
- Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Min Zhao, Kaushik Gala, Rajendran Panda:
Statistical delay computation considering spatial correlations. 271-276 - Emrah Acar, Ravishankar Arunachalam, Sani R. Nassif:
Predicting short circuit power from timing models. 277-282 - Zhanhai Qin, Chung-Kuan Cheng:
RCLK-VJ network reduction with Hurwitz polynomial approximation. 283-291
Symbolic simulation and verification
- George F. Viamontes, Manoj Rajagopalan, Igor L. Markov, John P. Hayes:
Gate-level simulation of quantum circuits. 295-301 - Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Manish Pandey, Magdy S. Abadir:
Enhanced symbolic simulation for efficient verification of embedded array systems. 302-307 - Edmund M. Clarke, Daniel Kroening:
Hardware verification using ANSI-C programs as a reference. 308-311 - Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
Evaluation of multiple-output logic functions using decision diagrams. 312-315
Modeling for floorplan
- Satoshi Tayu:
A simulated annealing approach with sequence-pair encoding using a penalty function for the placement problem with boundary constraints. 319-324 - Chin-Chih Chang, Jason Cong, Xin Yuan:
Multi-level placement for large-scale mixed-size IC designs. 325-330 - Chikaaki Kodama, Kunihiro Fujiyoshi:
Selected sequence-pair: an efficient decodable packing representation in linear time using sequence-pair. 331-337 - Changwen Zhuang, Keishi Sakanushi, Liyan Jin, Yoji Kajitani:
An extended representation of Q-sequence for optimizing channel-adjacency and routing-cost. 338-341 - De-Sheng Chen, Chang-Tzu Lin, Yiwen Wang:
Non-slicing floorplans with boundary constraints using generalized polish expression. 342-345
(Special session) panel discussion: anatomy of platform-based design: is it the savior of UDSM SoC design crisis?
- Tadahiko Nakamura, Takahide Inoue, Bob Altizer, Ken Chen, Jun Iwamura, Masasuke Kishi, Grant Martin, Augusto De Oliveira:
Anatomy of platform-based design: is it the savior of UDSM SoC design crisis? 349
Reconfigurable systems
- Hao Li, Wai-Kei Mak, Srinivas Katkoori:
Efficient LUT-based FPGA technology mapping for power minimization. 353-358 - Soheil Ghiasi, Majid Sarrafzadeh:
Optimal reconfiguration sequence management. 359-365 - Jiping Liu, Hongbing Fan, Yu-Liang Wu:
On improving FPGA routability applying multi-level switch boxes. 366-369 - Koji Nakano, Etsuko Takamichi:
An image retrieval system using FPGAs. 370-373 - Gary Spivey, Shuvra S. Bhattacharyya, Kazuo Nakajima:
Logic foundry: rapid prototyping of FPGA-based DSP systems. 374-381
Design methodologies for leading edge low-power design
- Luca Benini:
Advanced power management techniques: going beyond intelligent shutdown. 385-389 - Toshihiro Hattori:
Design methodology of low-power microprocessors. 390-393 - Tsuneo Tsukahara, Mitsuru Harada, Mamoru Ugajin, Junichi Kodate, Akihiro Yamagishi:
Design methodology of low-power CMOS RF-ICs. 394-399 - Ashish Srivastava, Dennis Sylvester:
Minimizing total power by simultaneous Vdd/Vth assignment. 400-403 - Takeo Yasuda, Kohji Hosokawa:
A low power CMOS circuit with Variable Souce Scheme (VSCMOS). 404-407
Performance driven floorplan
- Keith W. C. Wong, Evangeline F. Y. Young:
Fast buffer planning and congestion optimization in interconnect-driven floorplanning. 411-416 - Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou:
Interconnect-driven floorplanning by searching alternative packings. 417-422 - Katherine Shu-Min Li, Yih-Huai Cherng, Yao-Wen Chang:
Noise-aware buffer planning for interconnect-driven floorplanning. 423-426 - Hung-Ming Chen, Li-Da Huang, I-Min Liu, Minghorng Lai, D. F. Wong:
Floorplanning with power supply noise avoidance. 427-430 - Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao:
Simultaneous floorplanning and buffer block planning. 431-434 - Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
A buffer planning algorithm based on dead space redistribution. 435-438
(Special session) invited talks: virtual core based reuse methodology for SoC design
- Michiaki Muraoka, Hideyuki Hamada, Hiroaki Nishi, Toshihiko Tada, Yoichi Onishi, Toshinori Hosokawa, Kenji Yoshida:
VCore-based design methodology. 441-445 - Hiroaki Nishi, Michiaki Muraoka, Rafael K. Morizawa, Hideaki Yokota, Hideyuki Hamada:
Synthesis for SoC architecture using VCores. 446-452 - Yoichi Onishi, Michiaki Muraoka, Makoto Utsuki, Naoyuki Tsubaki:
VCore-based platform for SoC design. 453-458 - Rafael K. Morizawa, Kazuo Tanaka, Keisuke Watanabe, Yuji Kaitsu, Shoji Hanamura, Takao Shinsha, Michiaki Muraoka:
VCDS tool demonstration. 459
(Special session) invited talks + panel discussion: adaptive computing: what can it do, where can it go?
- Robert Reuss, Jose L. Muñoz, Toshiaki Miyazaki, Nader Bagherzadeh, Prith Banerjee, Brad L. Hutchings, Brian Schott:
Adaptive computing: what can it do, where can it go? 463 - Jose L. Muñoz:
DARPA's adaptive computing systems program. 464 - Brian Schott, Peter Bellows, Matthew French, Robert Parker:
Applications of adaptive computing systems for signal processing challenges. 465-470 - Haitao Du, Marcos Sánchez-Élez, Nozar Tabrizi, Nader Bagherzadeh, Manuel Lois Anido, Milagros Fernández:
Interactive ray tracing on reconfigurable SIMD MorphoSys. 471-476 - Prith Banerjee:
An overview of a compiler for mapping MATLAB programs onto FPGAs. 477-482 - K. Scott Hemmert, Brad L. Hutchings:
Issues in debugging highly parallel FPGA-based applications derived from source code. 483-488
Leading edge design examples
- Jae-Jin Lee, Gi-Yong Song:
Implementation of the super-systolic array for convolution. 491-494 - Ming-Cheng Sun, Chih-Pin Su, Chih-Tsun Huang, Cheng-Wen Wu:
Design of a scalable RSA and ECC crypto-processor. 495-498 - A. Bianco, Alberto Dassatti, Maurizio Martina, Andrea Molino, Fabrizio Vacca:
A reconfigurable, power-scalable rake receiver IP for W-CDMA. 499-502 - Woopyo Jeong, Kaushik Roy:
Robust high-performance low-power carry select adder. 503-506 - Henrik Eriksson, Per Larsson-Edefors, Tomas Henriksson, Christer Svensson:
Full-custom vs. standard-cell design flow: an adder case study. 507-510 - Jiajing Wang, Qianling Zhang:
A 500-MHz low-power five-port CMOS register file. 511-514 - Ning-Yaun Ker, Chung-Ho Chen:
An effective SDRAM power mode management scheme for performance and energy sensitive embedded systems. 515-518 - Sang-Hyuk Lee, Il-kwan Kim, Lynn Choi:
Branch predictor design and performance estimation for a high performance embedded microprocessor. 519-522
Design space exploration
- Christian Haubelt, Jürgen Teich:
Accelerating design space exploration using pareto-front arithmetics. 525-531 - Yun Cao, Hiroto Yasuura:
Quality-driven design by bitwidth optimization for video applications. 532-537 - Shun-Wen Cheng:
Arbitrary long digit integer sorter HW/SW co-design. 538-543
(Special session) panel discussion: roles of funding agencies in technology-driven economic development
- Kazuo Nakajima, Brian Schott, Tokinori Kozawa, Jose L. Muñoz, Wolfgang Rosenstiel, Sakae Takahashi, Chen-Wen Wu:
Roles of funding agencies in technology-driven economic development. 547
(Special session) invited talk: legal protection for semiconductor intellectual property
- Yoichi Oshima:
Legal protection for semiconductor Intellectual Property (IP). 551-555
(Special session) presentation and poster session: university LSI design contest
- Ming-Chih Chen, Shen-Fu Hsiao, Cheng-Hsien Yang:
Design and implementation of a video-oriented network-interface-card system. 559-560 - Chih-Pin Su, Tsung-Fu Lin, Chih-Tsun Huang, Cheng-Wen Wu:
A highly efficient AES cipher chip. 561-562 - Tomas Henriksson, Dake Liu:
Implementation of fast CRC calculation. 563-564 - Chetan Despande, Tom Chen:
Design of a CMOS test chip for package models and I/O characteristics verification. 565-566 - Masanori Fujibayashi, Toshiyuki Nozawa, Takahiro Nakayama, Kenji Mochizuki, Koji Kotani, Shigetoshi Sugawa, Tadahiro Ohmi:
A still image encoder based on adaptive resolution vector quantization employing needless calculation elimination architecture. 567-568 - K. Kalyan Chakravarthy, M. B. Srinivas:
Speech encoding and encryption in VLSI. 569-570 - Chiaki Kon, Naohiko Shimizu:
The design of an i8080A instruction compatible processor with extended memory address. 571-572 - Tomoaki Kouyama, Hibiki Nano, Chiaki Kon, Naohiko Shimizu:
The design of a USB device controller IYOYOYO. 573-574 - Kenta Yasufuku, Riku Ogawa, Keisuke Iwai, Hideharu Amano:
MAPLE chip: a processing element for a static scheduling centric multiprocessor. 575-576 - Kazuo Sakiyama, Patrick Schaumont, Ingrid Verbauwhede:
Finding the best system design flow for a high-speed JPEG encoder. 577-578 - Haruyasu Hayasaka, Hiroaki Haramiishi, Naohiko Shimizu:
The design of PCI bus interface. 579-580 - Ja-Sheng Liu, I-Hsin Chen, Yi-Chen Tsai, Shyh-Jye Jou:
Low-power digital CDMA receiver. 581-582 - Jeroen De Maeyer, Harald Devos, Wim Meeus, Peter Verplaetse, Dirk Stroobandt:
Hardware implementation of an EAN-13 bar code decoder. 583-584 - Yukihiro Kato, Tomokazu Morita:
Error correction circuit using difference-set cyclic code. 585-586 - I. Vijay Kumar, M. B. Srinivas:
Design of a digital CDMA receiver. 587-588 - Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera:
Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologies. 589-590 - Tetsushi Koide, Hans Jürgen Mattausch, Yuji Yano, Takayuki Gyohten, Yoshihiro Soda:
A nearest-hamming-distance search memory with fully parallel mixed digital-analog match circuitry. 591-592
System-level power issues
- Josef Haid, Gerald Kaefer, Christian Steger, Reinhold Weiss:
Run-time energy estimation in system-on-a-chip designs. 595-599 - Praveen Kalla, Jörg Henkel, Xiaobo Sharon Hu:
SEA: fast power estimation for micro-architectures. 600-605 - Xun Liu, Marios C. Papaefthymiou:
HyPE: hybrid power estimation for IP-based programmable systems. 606-609 - Chih-Yang Hsu, Chien-Nan Jimmy Liu, Jing-Yang Jou:
An efficient IP-level power model for complex digital circuits. 610-613 - Yu-Min Lee, Charlie Chung-Ping Chen:
A hierarchical analysis methodology for chip-level power delivery with realizable model reduction. 614-618
(Special session) invited talks: design methodologies for 50M gate ASICs
- Chin-Chih Chang, Jason Cong, Min Xie:
Optimality and scalability study of existing placement algorithms. 621-627 - Jürgen Koehl, David E. Lackey, George W. Doerre:
IBM's 50 Million gate ASICs. 628-634 - Wei-Jin Dai, Dennis Jen-Hsin Huang, Chin-Chih Chang, Michel Courtoy:
Silicon virtual prototyping: the new cockpit for nanometer chip design. 635-639 - Alok Mehrotra, Lukas P. P. P. van Ginneken, Yatin Trivedi:
Design flow and methodology for 50M gate ASIC. 640-647
(Special session) invited talks: mixed signal test
- Hak-soo Yu, Jacob A. Abraham, Sungbae Hwang, Jeongjin Roh:
Efficient loop-back testing of on-chip ADCs and DACs. 651-656 - Chauchin Su, Wei-Juo Wang, Chih-Hu Wang, I. S. Tseng:
A novel LCD driver testing technique using logic test channels. 657-662 - Salvador Mir, Luís Rolíndez, Christian Domigues, Libor Rufer:
An implementation of memory-based on-chip analogue test signal generation. 663-668 - Chee-Kian Ong, Kwang-Ting (Tim) Cheng, Li-C. Wang:
Delta-sigma modulator based mixed-signal BIST architecture for SoC. 669-674
Embedded systems: hardware/software design methodology and optimization
- Akira Kawaguchi:
Capturing and analyzing requirement: in case of software and applying to hardware. 677-682 - Jaehwan Lee, Vincent John Mooney III, Anders Daleby, Karl Ingström, Tommy Klevin, Lennart Lindh:
A comparison of the RTU hardware RTOS with a hardware/software RTOS. 683-688 - Che-Tai Lee, Zeng-Wei Hong, Jim-Min Lin:
Linux kernel customization for embedded systems by using call graph approach. 689-692 - Dexin Li, Pai H. Chou, Nader Bagherzadeh:
Topology selection for energy minimization in embedded networks. 693-696
Design validation techniques
- Julia Dushina, Mike Benjamin, Daniel Geist:
Semi-formal test generation and resolving a temporal abstraction problem in practice: industrial application. 699-704 - Anurag Tiwari, Karen A. Tomko:
Scan-chain based watch-points for efficient run-time debugging and verification of FPGA designs. 705-711 - Edwin Naroska, Shanq-Jang Ruan, Chia-Lin Ho, Said Mchaalia, Feipei Lai, Uwe Schwiegelshohn:
A novel approach for digital waveform compression. 712-715 - Daniel Eckerbert, Per Larsson-Edefors:
A deep submicron power estimation methodology adaptable to variations between power characterization and estimation. 716-719
Placement
- Zhuoyuan Li, Weimin Wu, Xianlong Hong:
Congestion driven incremental placement algorithm for standard cell layout. 723-728 - Chin Ngai Sze, Ting-Chi Wang:
Performance-driven multi-level clustering for combinational circuits. 729-740 - Jinan Lou, Wei Chen:
Cross talk driven placement. 735-740 - Sheqin Dong, Xianlong Hong, Xin Qi, Ruijie Wang, Song Chen, Jun Gu:
VLSI module placement with pre-placed modules and considering congestion using solution space smoothing. 741-744 - Wenting Hou, Xianlong Hong, Weimin Wu, Yici Cai:
A path-based timing-driven quadratic placement algorithm. 745-748
Test issues for deep sub-micron design
- Jing-Jia Liou, Li-C. Wang, Angela Krstic, Kwang-Ting Cheng:
Experience in critical path selection for deep sub-micron delay test and timing validation. 751-756 - Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka, Shinichi Yosimura:
On effective criterion of path selection for delay testing. 757-762 - Yasuo Sato, Motoyuki Sato, Koki Tsutsumida, Masatoshi Kawashima, Kazumi Hatayama, Kazuyuki Nomoto:
DFT timing design methodology for at-speed BIST. 763-768 - Tim McDougall, Atanas N. Parashkevov, Simon Jolly, Juhong Zhu, Jing Zeng, Carol Pyron, Magdy S. Abadir:
An automated method for test model generation from switch level circuits. 769-774
Analog circuits design and methodology
- Florin Balasa, Sarat C. Maruvada, Karthik Krishnamoorthy:
Using red-black interval trees in device-level analog placement with symmetry constraints. 777-782 - Jens Lienig, Göran Jerke:
Current-driven wire planning for electromigration avoidance in analog circuits. 783-788 - Sheldon X.-D. Tan, Chuanjin Richard Shi:
Efficient DDD-based term generation algorithm for analog circuit behavioral modeling. 789-794 - Chih-Hsien Lin, Chung-Hong Wang, Shyh-Jye Jou:
5Gbps serial link transmitter with pre-emphasis. 795-800
Synthesis for power performance optimization
- Ali Iranli, Peyman Rezvani, Massoud Pedram:
Low power synthesis of finite state machines with mixed D and T flip-flops. 803-808 - Yunjian Jiang, Robert K. Brayton:
Don't cares in logic minimization of extended finite state machines. 809-815 - Euiseok Kim, Dong-Ik Lee, Hiroshi Saito, Hiroshi Nakamura, Jeong-Gun Lee, Takashi Nanya:
Performance optimization of synchronous control units for datapaths with variable delay arithmetic units. 816-819 - Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy:
Integer linear programming-based synthesis of skewed logic circuits. 820-823
Routing
- Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky:
Highly scalable algorithms for rectilinear and octilinear Steiner trees. 827-833 - Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Chung-Kuan Cheng, Jun Gu:
UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing. 834-839 - Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng:
The Y-architecture: yet another on-chip interconnect solution. 840-847 - Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu:
A novel timing-driven global routing algorithm considering coupling effects for high performance circuit design. 847-850 - Jai-Ming Lin, Song-Ra Pan, Yao-Wen Chang:
Graph matching-based algorithms for array-based FPGA segmentation design and routing. 851-854
DFT optimizations
- Puneet Gupta, Andrew B. Kahng, Stefanus Mantik:
Routing-aware scan chain ordering. 857-862 - Youhua Shi, Zhe Zhang:
Multiple test set generation method for LFSR-based BIST. 863-868 - Kenichi Ichino, Ko-ichi Watanabe, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki:
A seed selection procedure for LFSR-based random pattern generators. 869-874 - Samir Roy, Ujjwal Maulik, Sanghamitra Bandyopadhyay, Subhadip Basu, Biplab Kumar Sikdar:
Efficient BIST design for sequential machines using FiF-FoF values in machine states. 875-878 - Chakunta Venkata Guru Rao, Dipanwita Roy Chowdhury:
A new design-for-test technique for reducing SOC test time. 879-882
RF circuits design and methodology
- Xinyu Wu, Zaiman Chen, Jinmei Lai, Qianling Zhang, Omar Wing, Junyan Ren:
Periodic steady-state analysis of coupled ODE-AE-CGE systems for MOS RF autonomous circuit simulation. 885-890 - Xin Li, Peng Li, Yang Xu, Robert Dimaggio, Lawrence T. Pileggi:
A frequency separation macromodel for system-level simulation of RF circuits. 891-896 - Peng Li, Lawrence T. Pileggi:
Nonlinear distortion analysis via linear-centric models. 897-903 - Jinho Park, Kiyong Choi, David J. Allstot:
Parasitic-aware design and optimization of a fully integrated CMOS wideband amplifier. 904-907
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