"Layout Techniques for Minimizing On-Chip Interconnect Self Inductance."

Yehia Massoud et al. (1998)

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DOI: 10.1145/277044.277194

access: closed

type: Conference or Workshop Paper

metadata version: 2023-05-08

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Yehia Massoud, Steve S. Majors, Tareq Bustami, Jacob K. White:
Layout Techniques for Minimizing On-Chip Interconnect Self Inductance. DAC 1998: 566-571

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