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ORCID"Layout Techniques for Minimizing On-Chip Interconnect Self Inductance."
Yehia Massoud et al. (1998)
- Yehia Massoud, Steve S. Majors, Tareq Bustami, Jacob K. White:
Layout Techniques for Minimizing On-Chip Interconnect Self Inductance. DAC 1998: 566-571
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