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ORCID15th ASYNC 2009: Chapel Hill, NC, USA
- 15th IEEE Symposium on Asynchronous Circuits and Systems, ASYNC 2009, Chapel Hill, NC, USA, May 17-20, 2009. IEEE Computer Society 2009, ISBN 978-1-4244-3933-1
- Eslam Yahya, Oussama Elissati
, Hatem M. Zakaria, Laurent Fesquet, Marc Renaudin:
Programmable/Stoppable Oscillator Based on Self-Timed Rings. 3-12 - Yvain Thonnart, Edith Beigné, Pascal Vivet:
Design and Implementation of a GALS Adapter for ANoC Based Architectures. 13-22 - Jian Wu, Steve B. Furber, Jim D. Garside:
A Programmable Adaptive Router for a GALS Parallel System. 23-31 - William John Bainbridge, Sean James Salisbury:
Glitch Sensitivity and Defense of Quasi Delay-Insensitive Network-on-Chip Links. 35-44 - Scott Fairbanks:
The Lackey Self-Timed Switch-Fabric Design Framework. 45-54 - Joseph Lin, Kwabena Boahen:
A Delay-Insensitive Address-Event Link. 55-62 - Sean Keller, Michael Katelman, Alain J. Martin:
A Necessary and Sufficient Timing Assumption for Speed-Independent Circuits. 65-76 - Yebin Shi, Steve B. Furber, Jim D. Garside, Luis A. Plana:
Fault Tolerant Delay Insensitive Inter-chip Communication. 77-84 - Jonathan Dama, Andrew Lines:
GHz Asynchronous SRAM in 65nm. 85-94 - Andrey Mokhov, Crescenzo D'Alessandro, Alex Yakovlev:
Synthesis of Multiple Rail Phase Encoding Circuits. 95-104 - Stanislavs Golubcovs, Delong Shang, Fei Xia, Andrey Mokhov, Alex Yakovlev:
Modular Approach to Multi-resource Arbiter Design. 107-116 - Ian W. Jones, Suwen Yang, Mark R. Greenstreet:
Synchronizer Behavior and Analysis. 117-126 - Gottfried Fuchs, Matthias Függer, Andreas Steininger:
On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation Scheme. 127-136 - William B. Toms, Doug A. Edwards:
Prime Indicants: A Synthesis Method for Indicating Combinational Logic Blocks. 139-150 - Kenneth S. Stevens, Yang Xu, Vikas S. Vij:
Characterization of Asynchronous Templates for Integration into Clocked CAD Flows. 151-161 - Alexander B. Smirnov, Alexander Taubin:
Heuristic Based throughput Analysis and Optimization of Asynchronous Pipelines. 162-172 - Maurizio Tranchero, Leonardo Maria Reyneri, Arjan Bink, Mark de Wit:
An Automatic Approach to Generate Haste Code from Simulink Specifications. 175-184 - Sune Fallgaard Nielsen, Jens Sparsø, Jonas Braband Jensen, Johan Sebastian Rosenkilde Nielsen:
A Behavioral Synthesis Frontend to the Haste/TiDE Design Flow. 185-194 - Gennette Gill, Montek Singh:
Bottleneck Analysis and Alleviation in Pipelined Systems: A Fast Hierarchical Approach. 195-205 - Masashi Imai, Kouei Takada, Takashi Nanya:
Fine-Grain Leakage Power Reduction Method for m-out-of-n Encoded Circuits Using Multi-threshold-Voltage Transistors. 209-216 - Christopher LaFrieda, Rajit Manohar:
Reducing Power Consumption with Relaxed Quasi Delay-Insensitive Circuits. 217-226
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