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ORCIDAndreas Steininger
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- affiliation: TU Wien, Vienna, Austria
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2020 – today
- 2022
[j29]Jürgen Maier
, Christian Hartl-Nesic, Andreas Steininger:
Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 1013-1026 (2022)- [c92]Zaheer Tabassam, Syed Rameez Naqvi, Andreas Steininger:
AµFLIPS: An Asynchronous Microprocessor With FLexIbly-timed Pipeline Stages. DDECS 2022: 32-37 - [c91]Florian Huemer, Robert Najvirt, Andreas Steininger:
On SAT-Based Model Checking of Speed-Independent Circuits. DDECS 2022: 100-105 - 2021
- [c90]Patrick Behal, Florian Huemer, Robert Najvirt, Andreas Steininger, Zaheer Tabassam:
Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles. ASYNC 2021: 25-33 - [c89]Raghda El Shehaby, Andreas Steininger:
Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines. DDECS 2021: 63-68 - [c88]Patrick Behal, Florian Huemer, Robert Najvirt, Andreas Steininger:
An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits. DSD 2021: 541-548 - [e3]Muhammad Shafique, Andreas Steininger, Lukás Sekanina, Milos Krstic, Goran Stojanovic, Vojtech Mrazek:
24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021. IEEE 2021, ISBN 978-1-6654-3595-6 [contents] - 2020
- [c87]Florian Huemer, Andreas Steininger:
Timing Domain Crossing using Muller Pipelines. ASYNC 2020: 44-53 - [c86]Wolfgang Duer, Andreas Steininger:
Merging Redundant Crystal Oscillators into a Fault-Tolerant Clock. DDECS 2020: 1-6 - [c85]Raghda El Shehaby, Andreas Steininger:
On the Effects of Permanent Faults in QDI Circuits - A Quantitative Perspective. ICCD 2020: 441-444 - [i6]Jürgen Maier, Andreas Steininger:
Online Test Vector Insertion: A Concurrent Built-In Self-Testing (CBIST) Approach for Asynchronous Logic. CoRR abs/2006.04577 (2020) - [i5]Andreas Steininger, Jürgen Maier, Robert Najvirt:
The Metastable Behavior of a Schmitt-Trigger. CoRR abs/2006.08319 (2020) - [i4]Andreas Steininger, Robert Najvirt, Jürgen Maier:
Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? CoRR abs/2006.08415 (2020) - [i3]Jürgen Maier, Andreas Steininger:
Efficient Metastability Characterization for Schmitt-Triggers. CoRR abs/2006.14001 (2020)
2010 – 2019
- 2019
- [j28]Thomas Polzer, Florian Huemer, Andreas Steininger:
An Experimental Study of Metastability-Induced Glitching Behavior. J. Circuits Syst. Comput. 28(Supplement-1): 1940006:1-1940006:21 (2019) - [c84]Jürgen Maier, Andreas Steininger:
Efficient Metastability Characterization for Schmitt-Triggers. ASYNC 2019: 124-133 - [c83]Andrew Paverd, Marcus Völp, Ferdinand Brasser, Matthias Schunter, N. Asokan, Ahmad-Reza Sadeghi, Paulo Jorge Esteves Veríssimo, Andreas Steininger, Thorsten Holz:
Sustainable Security & Safety: Challenges and Opportunities. CERTS 2019: 4:1-4:13 - [c82]Zoran Stamenkovic, Alberto Bosio, György Cserey, Ondrej Novák, Witold A. Pleskacz, Lukás Sekanina, Andreas Steininger, Goran Stojanovic, Viera Stopjaková:
International Symposium on Design and Diagnostics of Electronic Circuits and Systems. ITC 2019: 1-4 - 2018
- [j27]Thomas Polzer, Florian Huemer, Andreas Steininger:
Refined metastability characterization using a time-to-digital converter. Microelectron. Reliab. 80: 91-99 (2018) - [c81]Florian Huemer, Andreas Steininger:
Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication. ASYNC 2018: 17-25 - [c80]Florian Huemer, Thomas Polzer, Andreas Steininger:
Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA. DDECS 2018: 141-146 - [c79]Markus Schütz, Andreas Steininger, Florian Huemer, Jakob Lechner:
State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration. DFT 2018: 1-6 - 2017
- [j26]Andreas Steininger, Adam Pawlak, Viera Stopjaková:
Foreword. J. Circuits Syst. Comput. 26(8): 1702001:1-1702001:1 (2017) - [j25]Thomas Polzer, Andreas Steininger:
A Model for the Metastability Delay of Sequential Elements. J. Circuits Syst. Comput. 26(8): 1740010:1-1740010:22 (2017) - [j24]Varadan Savulimedu Veeravalli, Andreas Steininger, Ulrich Schmid:
A versatile architecture for long-term monitoring of single-event transient durations. Microprocess. Microsystems 53: 130-144 (2017) - [c78]Robert Najvirt, Thomas Polzer, Andreas Steininger:
Measuring Metastability with Free-Running Clocks. ASYNC 2017: 18-24 - [c77]Marko S. Andjelkovic, Milos Krstic, Rolf Kraemer, Varadan Savulimedu Veeravalli, Andreas Steininger:
A Critical Charge Model for Estimating the SET and SEU Sensitivity: A Muller C-Element Case Study. ATS 2017: 82-87 - [c76]Thomas Polzer, Florian Huemer, Andreas Steininger:
Measuring metastability using a time-to-digital converter. DDECS 2017: 116-121 - [c75]Bernhard Fritz, Andreas Steininger, Václav Simek, Varadan Savulimedu Veeravalli:
Setup for an Experimental Study of Radiation Effects in 65nm CMOS. DSD 2017: 329-336 - 2016
- [j23]Thomas Polzer, Robert Najvirt, Florian Beck, Andreas Steininger:
On the Appropriate Handling of Metastable Voltages in FPGAs. J. Circuits Syst. Comput. 25(3): 1640020:1-1640020:25 (2016) - [c74]Andreas Steininger, Jürgen Maier, Robert Najvirt:
The Metastable Behavior of a Schmitt-Trigger. ASYNC 2016: 57-64 - [c73]Thomas Polzer, Andreas Steininger:
A general approach for comparing metastable behavior of digital CMOS gates. DDECS 2016: 56-61 - [c72]Andreas Steininger, Robert Najvirt, Jürgen Maier:
Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? DSD 2016: 372-379 - [c71]Varadan Savulimedu Veeravalli, Andreas Steininger:
Design and Physical Implementation of a Target ASIC for SET Experiments. DSD 2016: 694-697 - [c70]Varadan Savulimedu Veeravalli, Andreas Steininger:
Study of a delayed single-event effect in the Muller C-element. ETS 2016: 1-2 - [c69]Florian Huemer, Jakob Lechner, Andreas Steininger:
A new coding scheme for fault tolerant 4-phase delay-insensitive codes. ICCD 2016: 392-395 - 2015
- [j22]Danny Dolev, Matthias Függer, Christoph Lenzen, Ulrich Schmid, Andreas Steininger:
Fault-tolerant Distributed Systems in Hardware. Bull. EATCS 116 (2015) - [j21]Peter Rössler, Andreas Steininger:
Digitale Mikroelektronik in Österreich. Elektrotech. Informationstechnik 132(6): 257-258 (2015) - [j20]Andreas Steininger, Horst Zimmermann, Axel Jantsch, Michael Hofbauer, Ulrich Schmid, Kurt Schweiger, Varadan Savulimedu Veeravalli:
Building reliable systems-on-chip in nanoscale technologies. Elektrotech. Informationstechnik 132(6): 301-306 (2015) - [j19]Stefan Resch, Andreas Steininger, Christoph Scherrer:
A composable real-time architecture for replicated railway applications. J. Syst. Archit. 61(9): 472-485 (2015) - [c68]Robert Najvirt, Andreas Steininger:
How to Synchronize a Pausible Clock to a Reference. ASYNC 2015: 9-16 - [c67]Robert Najvirt, Thomas Polzer, Florian Beck, Andreas Steininger:
Containment of Metastable Voltages in FPGAs. DDECS 2015: 197-202 - [c66]Varadan Savulimedu Veeravalli, Andreas Steininger:
Reliable and Continuous Measurement of SET Pulse Widths. DSD 2015: 181-188 - [c65]Thomas Polzer, Andreas Steininger:
Measuring the Distribution of Metastable Upsets over Time. DSD 2015: 189-196 - [c64]Thomas Polzer, Andreas Steininger:
Enhanced Metastability Characterization Based on AC Analysis. DSD 2015: 722-729 - [c63]Robert Najvirt, Andreas Steininger:
A pausible clock with crystal oscillator accuracy. ECCTD 2015: 1-4 - [c62]Jakob Lechner, Andreas Steininger, Florian Huemer:
Methods for analysing and improving the fault resilience of delay-insensitive codes. ICCD 2015: 519-526 - [c61]Robert Najvirt, Andreas Steininger:
A versatile and reliable glitch filter for clocks. PATMOS 2015: 140-147 - 2014
- [j18]Danny Dolev, Matthias Függer, Markus Posch, Ulrich Schmid, Andreas Steininger, Christoph Lenzen:
Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip. J. Comput. Syst. Sci. 80(4): 860-900 (2014) - [j17]Thomas Reinbacher, Jörg Brauer, Martin Horauer, Andreas Steininger, Stefan Kowalewski:
Runtime verification of microcontroller binary code. Sci. Comput. Program. 80: 109-129 (2014) - [c60]Syed Rameez Naqvi, Andreas Steininger:
A tree arbiter cell for high speed resource sharing in asynchronous environments. DATE 2014: 1-6 - [c59]Jürgen Maier, Andreas Steininger:
Online test vector insertion: A concurrent built-in self-testing (CBIST) approach for asynchronous logic. DDECS 2014: 33-38 - [c58]Andreas Steininger, Varadan Savulimedu Veeravalli, Dan Alexandrescu, Enrico Costenaro, Lorena Anghel:
Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example. ICCD 2014: 61-67 - [c57]Syed Rameez Naqvi, Jakob Lechner, Andreas Steininger:
Protection of Muller-Pipelines from transient faults. ISQED 2014: 123-131 - [c56]Varadan Savulimedu Veeravalli, Andreas Steininger, Ulrich Schmid:
Measuring SET pulsewidths in logic gates using digital infrastructure. ISQED 2014: 236-242 - [c55]Varadan Savulimedu Veeravalli, Andreas Steininger:
Architecture for monitoring SET propagation in 16-bit Sklansky adder. ISQED 2014: 412-419 - [c54]Robert Najvirt, Andreas Steininger:
Equivalence of clock gating and synchronization with applicability to GALS communication. PATMOS 2014: 1-8 - 2013
- [j16]Varadan Savulimedu Veeravalli, Thomas Polzer, Ulrich Schmid, Andreas Steininger, Michael Hofbauer, Kurt Schweiger, Horst Dietrich, Kerstin Schneider-Hornstein, Horst Zimmermann, Kay-Obbe Voss, Bruno Merk, Michael Hajek:
An infrastructure for accurate characterization of single-event transients in digital circuits. Microprocess. Microsystems 37(8-A): 772-791 (2013) - [c53]Syed Rameez Naqvi, Andreas Steininger, Jakob Lechner:
An SET Tolerant Tree Arbiter Cell. ASYNC 2013: 31-39 - [c52]Robert Najvirt, Syed Rameez Naqvi, Andreas Steininger:
Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs. ASYNC 2013: 115-123 - [c51]Thomas Polzer, Andreas Steininger:
An Approach for Efficient Metastability Characterization of FPGAs through the Designer. ASYNC 2013: 174-182 - [c50]Syed Rameez Naqvi, Robert Najvirt, Andreas Steininger:
A Multi-Credit Flow Control scheme for asynchronous NoCs. DDECS 2013: 153-158 - [c49]Thomas Polzer, Andreas Steininger:
Digital Late-Transition Metastability Simulation Model. DSD 2013: 121-128 - [c48]Thomas Polzer, Andreas Steininger:
SET propagation in micropipelines. PATMOS 2013: 126-133 - [c47]Thomas Polzer, Andreas Steininger:
Metastability characterization for muller C-elements. PATMOS 2013: 164-171 - [c46]Stefan Resch, Andreas Steininger, Christoph Scherrer:
Software Composability and Mixed Criticality for Triple Modular Redundant Architectures. SASSUR@SAFECOMP 2013 - 2012
- [c45]Paul Milbredt, Michael Glaß, Martin Lukasiewycz, Andreas Steininger, Jürgen Teich:
Designing FlexRay-based automotive architectures: A holistic OEM approach. DATE 2012: 276-279 - [c44]Varadan Savulimedu Veeravalli, Andreas Steininger:
Radiation-tolerant combinational gates - an implementation based comparison. DDECS 2012: 115-120 - [c43]Varadan Savulimedu Veeravalli, Thomas Polzer, Andreas Steininger, Ulrich Schmid:
Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip. DSD 2012: 8-17 - [c42]Syed Rameez Naqvi, Varadan Savulimedu Veeravalli, Andreas Steininger:
Protecting an Asynchronous NoC against Transient Channel Faults. DSD 2012: 264-271 - [c41]Thomas Polzer, Andreas Steininger, Jakob Lechner:
Muller C-Element Metastability Containment. PATMOS 2012: 103-112 - [i2]Danny Dolev, Matthias Függer, Christoph Lenzen, Markus Posch, Ulrich Schmid, Andreas Steininger:
FATAL+: A Self-Stabilizing Byzantine Fault-tolerant Clocking Scheme for SoCs. CoRR abs/1202.1925 (2012) - 2011
- [j15]Peter Tummeltshammer, Andreas Steininger:
Replicated processors on a single die - How independently do they fail? Elektrotech. Informationstechnik 128(6): 245-250 (2011) - [j14]Gottfried Fuchs, Andreas Steininger:
VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation. J. Electr. Comput. Eng. 2011: 936712:1-936712:23 (2011) - [c40]Thomas Reinbacher, Jörg Brauer, Martin Horauer, Andreas Steininger, Stefan Kowalewski:
Past Time LTL Runtime Verification for Microcontroller Binary Code. FMICS 2011: 37-51 - [c39]Thomas Reinbacher, Jörg Brauer, Daniel Schachinger, Andreas Steininger, Stefan Kowalewski:
Automated Test-Trace Inspection for Microcontroller Binary Code. RV 2011: 239-244 - [e2]Rolf Kraemer, Adam Pawlak, Andreas Steininger, Mario Schölzel, Jaan Raik, Heinrich Theodor Vierhaus:
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2011, Cottbus, Germany, April 13-15, 2011. IEEE Computer Society 2011, ISBN 978-1-4244-9755-3 [contents] - 2010
- [c38]Thomas Panhofer, Werner Friesenbichler, Andreas Steininger:
Reliability estimation and experimental results of a self-healing asynchronous circuit: A case study. AHS 2010: 91-98 - [c37]Marcus Jeitler, Jakob Lechner, Andreas Steininger:
Enhancing pipelined processor architectures with fast autonomous recovery of transient faults. DDECS 2010: 233-236 - [c36]Werner Friesenbichler, Thomas Panhofer, Andreas Steininger:
A deterministic approach for hardware fault injection in asynchronous QDI logic. DDECS 2010: 317-322 - [c35]Thomas Panhofer, Werner Friesenbichler, Andreas Steininger:
Implementation of self-healing asynchronous circuits at the example of a video-processing algorithm. DSN Workshops 2010: 125-130 - [c34]Thomas Reinbacher, Jörg Brauer, Martin Horauer, Andreas Steininger, Stefan Kowalewski:
Test-Case Generation for Embedded Binary Code Using Abstract Interpretation. MEMICS 2010: 101-108 - [e1]Elena Gramatová, Zdenek Kotásek, Andreas Steininger, Heinrich Theodor Vierhaus, Horst Zimmermann:
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010. IEEE Computer Society 2010, ISBN 978-1-4244-6612-2 [contents]
2000 – 2009
- 2009
- [j13]Babak Rahbaran, Andreas Steininger:
Is Asynchronous Logic More Robust Than Synchronous Logic?. IEEE Trans. Dependable Secur. Comput. 6(4): 282-294 (2009) - [j12]Matthias Függer, Eric Armengaud, Andreas Steininger:
Safely Stimulating the Clock Synchronization Algorithm in Time-Triggered Systems - a Combined Formal & Experimental Approach. IEEE Trans. Ind. Informatics 5(2): 132-146 (2009) - [c33]Gottfried Fuchs, Matthias Függer, Andreas Steininger:
On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation Scheme. ASYNC 2009: 127-136 - [c32]Eric Armengaud, Andreas Steininger:
Remote measurement of local oscillator drifts in FlexRay networks. DATE 2009: 1082-1087 - [c31]Peter Tummeltshammer, Andreas Steininger:
On the role of the power supply as an entry for common cause faults - An experimental analysis. DDECS 2009: 152-157 - [c30]Werner Friesenbichler, Andreas Steininger:
Soft Error Tolerant Asynchronous Circuits Based on Dual Redundant Four State Logic. DSD 2009: 100-107 - [c29]Peter Tummeltshammer, Andreas Steininger:
On the Risk of Fault Coupling over the Chip Substrate. DSD 2009: 325-332 - [c28]Peter Tummeltshammer, Andreas Steininger:
Power supply induced common cause faults-experimental assessment of potential countermeasures. DSN 2009: 449-457 - [c27]Thomas Polzer, Thomas Handl, Andreas Steininger:
A Metastability-Free Multi-synchronous Communication Scheme for SoCs. SSS 2009: 578-592 - 2008
- [j11]Kristian Ambrosch, Wilfried Kubinger, Martin Humenberger, Andreas Steininger:
Flexible Hardware-Based Stereo Matching. EURASIP J. Embed. Syst. 2008 (2008) - [j10]Eric Armengaud, Andreas Steininger, Martin Horauer:
Towards a Systematic Test for Embedded Automotive Communication Systems. IEEE Trans. Ind. Informatics 4(3): 146-155 (2008) - [c26]Kristian Ambrosch, Martin Humenberger, Wilfried Kubinger, Andreas Steininger:
Extending two non-parametric transforms for FPGA based stereo matching using bayer filtered cameras. CVPR Workshops 2008: 1-8 - [c25]Paul Milbredt, Andreas Steininger, Martin Horauer:
Automated Testing of FlexRay Clusters for System Inconsistencies in Automotive Networks. DELTA 2008: 533-538 - [c24]Gottfried Fuchs, Matthias Függer, Ulrich Schmid, Andreas Steininger:
Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip. DSD 2008: 242-249 - [c23]Wolfgang Forster, Christof Kutschera, Andreas Steininger, Karl M. Göschka:
Automated generation of explicit connectors for component based hardware/software interaction in embedded real-time systems. IPDPS 2008: 1-8 - [c22]Paul Milbredt, Martin Horauer, Andreas Steininger:
An investigation of the clique problem in FlexRay. SIES 2008: 200-207 - [i1]Andreas Steininger:
Error Containment in the Presence of Metastability. Fault-Tolerant Distributed Algorithms on VLSI Chips 2008 - 2007
- [j9]Ulrich Schmid, Andreas Steininger, Manfred Sust:
FIT-IT-Projekt DARTS: dezentrale fehlertolerante Taktgenerierung. Elektrotech. Informationstechnik 124(1-2): 3-8 (2007) - [c21]Kristian Ambrosch, Wilfried Kubinger, Martin Humenberger, Andreas Steininger:
Hardware implementation of an SAD based stereo vision algorithm. CVPR 2007 - [c20]Eric Armengaud, Andreas Steininger, Alexander Hanzlik:
The effect of quartz drift on convergence-average based clock synchronization. ETFA 2007: 1123-1130 - [c19]Thomas Kottke, Andreas Steininger:
A Fail-Silent Reconfigurable Superscalar Processor. PRDC 2007: 232-239 - 2006
- [c18]Christian El Salloum, Andreas Steininger, Peter Tummeltshammer, Werner Harter:
Recovery Mechanisms for Dual Core Architectures. DFT 2006: 380-388 - [c17]Markus Ferringer, Gottfried Fuchs, Andreas Steininger, Gerald Kempf:
VLSI Implementation of a Fault-Tolerant Distributed Clock Generation. DFT 2006: 563-571 - [c16]Martin Delvai, Andreas Steininger:
Solving the Fundamental Problem of Digital Design - A Systematic Review of Design Methods. DSD 2006: 131-138 - [c15]Thomas Kottke, Andreas Steininger:
A Reconfigurable Generic Dual-Core Architecture. DSN 2006: 45-54 - [c14]Eric Armengaud, Andreas Steininger, Martin Horauer:
Automatic Parameter Identi cation in FlexRay based Automotive Communication Networks. ETFA 2006: 897-904 - 2005
- [c13]Eric Armengaud, Andreas Steininger, Martin Horauer:
Efficient stimulus generation for testing embedded distributed systems the FlexRay example. ETFA 2005 - [c12]Eric Armengaud, Florian Rothensteiner, Andreas Steininger, Roman Pallierer, Martin Horauer, Martin Zauner:
A structured approach for the systematic test of embedded automotive communication systems. ITC 2005: 8 - 2004
- [j8]Thomas Kottke, Andreas Steininger:
A Generic Dual Core Architecture with Error Containment. Comput. Artif. Intell. 23(5): 517-535 (2004) - [c11]Babak Rahbaran, Andreas Steininger, Thomas Handl:
Built-in Fault Injection in Hardware - The FIDYCO Example. DELTA 2004: 327-332 - [c10]Babak Rahbaran, Matthias Függer, Andreas Steininger:
Embedded Real-Time-Tracer - An Approach with IDE. WISES 2004: 25-35 - 2003
- [j7]Karl Thaller, Andreas Steininger:
A transparent online memory test for simultaneous detection of functional faults and soft errors in memories. IEEE Trans. Reliab. 52(4): 413-422 (2003) - [j6]Christoph Scherrer, Andreas Steininger:
Dealing with dormant faults in an embedded fault-tolerant computer system. IEEE Trans. Reliab. 52(4): 512-522 (2003) - [c9]Martin Delvai, Wolfgang Huber, Peter P. Puschner, Andreas Steininger:
Processor Support for Temporal Predictability - The SPEAR Design Example. ECRTS 2003: 169-176 - [c8]Andreas Steininger, Babak Rahbaran, Thomas Handl:
Built-In Fault Injectors - The Logical Continuation of BIST? WISES 2003: 187-196 - 2002
- [j5]Andreas Steininger, Christoph Scherrer:
Identifying Efficient Combinations of Error Detection Mechanisms Based on Results of Fault Injection Experiments. IEEE Trans. Computers 51(2): 235-239 (2002) - [c7]Andreas Steininger, Johann Vilanek:
Using Offline and Online BIST to Improve System Dependability - The TTPC-C Example. ICCD 2002: 277- - 2001
- [c6]Andreas Steininger, Christoph Scherrer:
How to Tune the MTTF of a Fail-Silent System. DFT 2001: 418- - 2000
- [j4]Andreas Steininger:
Testing and built-in self-test - A survey. J. Syst. Archit. 46(9): 721-747 (2000) - [c5]Andreas Steininger, Christoph Scherrer:
How Does Resource Utilization Affect Fault Tolerance? DFT 2000: 251-256
1990 – 1999
- 1999
- [j3]