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ORCIDETW 2002: Corfu, Greece
- 7th European Test Workshop, ETW 2002, Corfu, Greece, May 26-29, 2002. IEEE Computer Society 2002, ISBN 0-7695-1715-3
- Gregory S. Spirakis:
Silicon technology advances and implications on test. 3 - Sandeep Kumar Goel, Erik Jan Marinissen
:
A novel test time reduction algorithm for test architecture design for core-based system chips. 7-12 - Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand:
Modeling gate oxide short defects in CMOS minimum transistors. 15-20 - Srikanth Arekapudi, Fei Xin, Jinzheng Peng, Ian G. Harris:
ATPG for timing-induced functional errors on trigger events in hardware-software systems. 23-28 - Andrzej Hlawiczka, Michal Kopec:
Dependable testing of compactor MISR: an imperceptible problem? 31-36 - Lars Schäfer, Rainer Dorsch, Hans-Joachim Wunderlich:
RESPIN++ - deterministic embedded test. 37-44 - Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran:
Novel ATPG algorithms for transition faults. 47-52 - Yun Shao, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara:
On selecting testable paths in scan designs. 53-58 - Sandeep Kumar Goel, Bart Vermeulen:
Data invalidation analysis for scan-based debug on multiple-clock system chips. 61-66 - Tiziana Margaria, Oliver Niese, Bernhard Steffen, Andrei Erochok:
System level testing of virtual switch (re-)configuration over IP. 67-72 - Jonathan Bradford, Hartmut Delong, Ilia Polian, Bernd Becker:
Simulating realistic bridging and crosstalk faults in an industrial setting. 75-80 - Hans A. R. Manhaeve, Joseph S. Vaccaro, Loren Benecke, David Prystasz:
A real world application used to implement a true IDDQ based test strategy (facts and figures). 81-86 - Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell:
A high accuracy triangle-wave signal generator for on-chip ADC testing. 89-94 - Martin John Burbidge, Frédéric Poullet, Jim Tijou, Andrew M. D. Richardson:
Investigations for minimum invasion digital only built-in "ramp" based test techniques for charge pump PLL's. 95-102 - Harald P. E. Vranken, Florian Meister, Hans-Joachim Wunderlich:
Combining deterministic logic BIST with test point insertion. 105-110 - Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu:
Dynamic test data transformations for average and peak power reductions. 113-118 - Erik Larsson, Hideo Fujiwara:
Power constrained preemptive TAM scheduling. 119-126
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