default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDHEART 2017: Bochum, Germany
- Diana Göhringer, Michael Hübner:
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2017, Bochum, Germany, June 7-9, 2017. ACM 2017, ISBN 978-1-4503-5316-8
Architecture & System I
- Yuma Sakakibara, Kohei Nakamura, Hiroki Matsutani:
An FPGA NIC Based Hardware Caching for Blockchain. 1:1-1:6 - Deshya Wijesundera, Achintha Ihalage, Alok Prakash, Thambipillai Srikanthan:
High Speed Performance Estimation of Embedded Hard-core Processors in FPGA-based SoCs. 2:1-2:6 - Kasho Yamamoto, Weiqiang Huang, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
:
A Time-Division Multiplexing Ising Machine on FPGAs. 3:1-3:6 - Jubee Tada, Masayuki Sato, Ryusuke Egawa:
An Adaptive Demotion Policy for High-Associativity Caches. 4:1-4:6
Design Methodology & Tools I
- Nina Engelhardt, Hayden Kwok-Hay So:
Towards Flexible Automatic Generation of Graph Processing Gateware. 5:1-5:6 - Charles Shelor, Krishna M. Kavi:
Dataflow based Near Data Computing Achieves Excellent Energy Efficiency. 6:1-6:6 - Mostafa Koraei, Magnus Jahre, S. Omid Fatemi:
DTP: Enabling Exhaustive Exploration of FPGA Temporal Partitions for Streaming HPC Applications. 7:1-7:11 - Yuto Ishikawa, Keitaro Yanai, Keisuke Koike, Takefumi Miyoshi, Hironori Nakajo:
Hardware Acceleration with Multi-Threading of Java-Based High Level Synthesis Tool. 8:1-8:6 - Takahiro Kaneda, Ryotaro Sakai, Naoki Nishikawa, Toshihiro Hanawa, Chiharu Tsuruta, Hideharu Amano:
Performance Evaluation of PEACH3: Field-Programmable Gate Array Switch for Tightly Coupled Accelerators. 9:1-9:6
Application I
- Lester Kalms, Khaled Mohamed, Diana Göhringer:
Accelerated Embedded AKAZE Feature Detection Algorithm on FPGA. 10:1-10:6 - Donald G. Bailey, Faisal Mahmood, Ulf Skoglund:
Reducing the Cost of Removing Border Artefacts in Fourier Transforms. 11:1-11:6 - Takaaki Miyajima, Kenichi Kubota, Naoyuki Fujita:
A porting and optimization of search for neighbour-particle in MPS method for GPU by using OpenACC. 12:1-12:6 - Yuhei Sugata, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota:
Acceleration of Publish/Subscribe Messaging in ROS-compliant FPGA Component. 13:1-13:6
Architecture & Applications
- Ryo Kamasaka, Yuichiro Shibata, Kiyoshi Oguri:
FPGA Implementation of A Graph Cut Algorithm For Stereo Vision. 14:1-14:6 - Sajjad Nouri, Jens Rettkowski, Diana Göhringer, Jari Nurmi:
HW/SW Co-design of an IEEE 802.11a/g Receiver on Xilinx Zynq SoC using High-Level Synthesis. 15:1-15:6 - Kentaro Sano, Shin Abiko, Tomohiro Ueno:
FPGA-based Stream Computing for High-Performance N-Body Simulation using Floating-Point DSP Blocks. 16:1-16:6 - Jiajun Li, Qiang Liu:
Neural Network Training Acceleration with PSO Algorithm on a GPU Using OpenCL. 17:1-17:6 - Motoki Amagasaki, Futoshi Murase, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi:
FPGA based ASIC Emulator with High Speed Optical Serial Links. 18:1-18:6
Poster Session I
- Shin Morishima, Masahiro Okazaki, Hiroki Matsutani:
A Case for Remote GPUs over 10GbE Network for VR Applications. 19:1-19:6 - Hiroyuki Noda, Ryotaro Sakai, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano:
Acceleration of the aggregation process in a Hall-thruster simulation using Intel FPGA SDK for OpenCL. 20:1-20:6 - Oliver Jakob Arndt, Christian Spindeldreier, Kevin Wohnrade, Daniel Pfefferkorn, Martin Neuenhahn, Holger Blume:
FPGA Accelerated NoC-Simulation: A Case Study on the Intel Xeon Phi Ringbus Topology. 21:1-21:6 - Yasunori Osana, Yohei Sakamoto:
Performance Evaluation of a CPU-FPGA Hybrid Cluster Platform Prototype. 22:1-22:6 - Morihiro Kuga, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi:
High-level Synthesis based on Parallel Design Patterns using a Functional Language. 23:1-23:6
Poster Session II
- Ioannis Stamoulias, Matthias Möller, Rene Miedema, Christos Strydis, Christoforos Kachris, Dimitrios Soudris:
High-Performance Hardware Accelerators for Solving Ordinary Differential Equations. 24:1-24:6 - Habib ul Hasan Khan, Thomas Grimm, Michael Hübner, Diana Göhringer:
Access Network Generation for Efficient Debugging of FPGAs. 25:1-25:6 - Masahiro Fukuda, Yasushi Inoguchi:
Probabilistic Strategies Based on Staged LSH for Speedup of Audio Fingerprint Searching with Ten Million Scale Database. 26:1-26:6 - Jose Raul Garcia Ordaz, Dirk Koch:
HLS Compilation for CPU Interlays. 27:1-27:6
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-14 20:48 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
