default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID9th HEART 2018: Toronto, ON, Canada
- Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2018, Toronto, ON, Canada, June 20-22, 2018. ACM 2018
Invited Papers
- Andrew C. Ling, Mohamed S. Abdelfattah, Shane O'Connell, Andrew Bitar, David Han, Roberto DiCecco, Suchit Subhaschandra, Chris N. Johnson, Dmitry Denisenko, Joshua Fender, Gordon R. Chiu:
Harnessing Numerical Flexibility for Deep Learning on FPGAs. 1:1-1:3 - Jongsok Choi, Ruolong Lian, Zhi Li, Andrew Canis, Jason Helge Anderson:
Accelerating Memcached on AWS Cloud FPGAs. 2:1-2:8
HW-SW Partitioning and Optimization Frameworks
- Deshya Wijesundera, Alok Prakash, Thilina Perera, Kalindu Herath, Thambipillai Srikanthan:
Wibheda+: Framework for Data Dependency-aware Multi-constrained Hardware-Software Partitioning in FPGA-based SoCs for IoT Applications. 3:1-3:6 - David Wilson, Greg Stitt, James Coole:
A Recurrently Generated Overlay Architecture for Rapid FPGA Application Development. 4:1-4:6 - Jinpil Lee, Tomohiro Ueno
, Mitsuhisa Sato, Kentaro Sano:
High-productivity Programming and Optimization Framework for Stream Processing on FPGA. 5:1-5:6
Acceleration
- Norihisa Fujita, Ryohei Kobayashi, Yoshiki Yamaguchi, Yuma Oobata, Taisuke Boku, Makito Abe, Kohji Yoshikawa, Masayuki Umemura:
Accelerating Space Radiative Transfer on FPGA using OpenCL. 6:1-6:7 - Ahmed Sanaullah, Martin C. Herbordt:
FPGA HPC using OpenCL: Case Study in 3D FFT. 7:1-7:6
Applications
- Kenji Kise:
Swap Based Merge Network for High Performance Sorting Accelerators. 8:1-8:7 - Andreea-Ingrid Cross, Liucheng Guo, Wayne Luk, Mark Salmon:
CJS: Custom Jacobi Solver. 9:1-9:6 - Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara:
Power Efficient Object Detector with an Event-Driven Camera on an FPGA. 10:1-10:6 - Yasmin Afsharnejad, Abdul-Amir Yassine, Omar Ragheb, Paul Chow, Vaughn Betz:
HLS-based FPGA Acceleration of Light Propagation Simulation in Turbid Media. 11:1-11:6
Architecture & Applications
- Bain Syrowik, Blair Fort, Stephen Dean Brown:
Use of CPU Performance Counters for Accelerator Selection in HLS-Generated CPU-Accelerator Systems. 12:1-12:6 - Takuya Kojima, Naoki Ando, Yusuke Matshushita, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano:
Real Chip Evaluation of a Low Power CGRA with Optimized Application Mapping. 13:1-13:6 - Piero Rivera Benois, Patrick Nowak, Udo Zölzer, Marcel Eckert, Bernd Klauer:
Low-Latency FIR Filter Structures Targeting FPGA Platforms. 14:1-14:7
Poster Session
- Zheming Jin, Hal Finkel:
A Case Study of Integer Sum Reduction using Atomics. 15:1-15:7 - Mokhles A. Mohsin, Darshika G. Perera:
An FPGA-Based Hardware Accelerator for K-Nearest Neighbor Classification for Machine Learning on Mobile Devices. 16:1-16:7 - Alan Ehret, Peter Jamieson, Michel A. Kinsy:
Scalable Open-Source Reconfigurable Architecture for Bacterial Quorum Sensing Simulations. 17:1-17:5 - Jesse Schmitz, Lei Zhang:
FPGA Hardware Implementation and Optimization for Neural Network based Chaotic System Design. 18:1-18:6 - Masoud Oveis Gharan, Gul N. Khan:
Flexible Reconfigurable On-chip Networks for Multi-core SoCs. 19:1-19:6 - Haoxuan Cheng, Shimpei Sato, Hiroki Nakahara:
A Performance Per Power Efficient Object Detector on an FPGA for Robot Operating System (ROS). 20:1-20:4
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-11-11 02:09 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
