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ORCIDStephen Dean Brown
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- affiliation: University of Toronto, Canada
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2010 – 2019
- 2018
[c64]Bain Syrowik, Blair Fort, Stephen Dean Brown:
Use of CPU Performance Counters for Accelerator Selection in HLS-Generated CPU-Accelerator Systems. HEART 2018: 12:1-12:6- 2017
- [j20]Jongsok Choi
, Stephen Dean Brown, Jason Helge Anderson:
From Pthreads to Multicore Hardware Systems in LegUp High-Level Synthesis for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2867-2880 (2017) - [c63]Kevin Nam, Blair Fort, Stephen Dean Brown:
FISH: Linux system calls for FPGA accelerators. FPL 2017: 1-4 - 2016
- [j19]Razvan Nane, Vlad Mihai Sima, Christian Pilato, Jongsok Choi, Blair Fort, Andrew Canis, Yu Ting Chen, Hsuan Hsiao, Stephen Dean Brown, Fabrizio Ferrandi, Jason Helge Anderson, Koen Bertels:
A Survey and Evaluation of FPGA High-Level Synthesis Tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1591-1604 (2016) - [c62]Jongsok Choi, Ruolong Lian, Stephen Dean Brown, Jason Helge Anderson:
A unified software approach to specify pipeline and spatial parallelism in FPGA hardware. ASAP 2016: 75-82 - [p1]Andrew Canis, Jongsok Choi, Blair Fort, Bain Syrowik, Ruolong Lian, Yu Ting Chen, Hsuan Hsiao, Jeffrey B. Goeders, Stephen Dean Brown, Jason Helge Anderson:
LegUp High-Level Synthesis. FPGAs for Software Programmers 2016: 175-190 - 2015
- [j18]Qijing Huang, Ruolong Lian, Andrew Canis, Jongsok Choi, Ryan Xi, Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson:
The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware. ACM Trans. Reconfigurable Technol. Syst. 8(3): 14:1-14:26 (2015) - [c61]Jongsok Choi, Stephen Dean Brown, Jason Helge Anderson:
Resource and memory management techniques for the high-level synthesis of software threads into parallel FPGA hardware. FPT 2015: 152-159 - 2014
- [c60]Blair Fort, Andrew Canis, Jongsok Choi, Nazanin Calagar, Ruolong Lian, Stefan Hadjis, Yu Ting Chen, Mathew Hall, Bain Syrowik, Tomasz S. Czajkowski, Stephen Dean Brown, Jason Helge Anderson:
Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis. EUC 2014: 120-129 - [c59]Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson:
Source-level debugging for FPGA high-level synthesis. FPL 2014: 1-8 - [c58]Andrew Canis, Stephen Dean Brown, Jason Helge Anderson:
Modulo SDC scheduling with recurrence minimization in high-level synthesis. FPL 2014: 1-8 - 2013
- [j17]Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Tomasz S. Czajkowski, Stephen Dean Brown, Jason Helge Anderson:
LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems. ACM Trans. Embed. Comput. Syst. 13(2): 24:1-24:27 (2013) - [j16]Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown:
Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAs. ACM Trans. Reconfigurable Technol. Syst. 6(4): 16:1-16:37 (2013) - [c57]Andrew Canis, Jongsok Choi, Blair Fort, Ruolong Lian, Qijing Huang, Nazanin Calagar, Marcel Gort, Jia Jun Qin, Mark Aldham, Tomasz S. Czajkowski, Stephen Dean Brown, Jason Helge Anderson:
From software to accelerators with LegUp high-level synthesis. CASES 2013: 18:1-18:9 - [c56]Andrew Canis, Jason Helge Anderson, Stephen Dean Brown:
Multi-pumping for resource reduction in FPGA high-level synthesis. DATE 2013: 194-197 - [c55]Qijing Huang, Ruolong Lian, Andrew Canis, Jongsok Choi, Ryan Xi, Stephen Dean Brown, Jason Helge Anderson:
The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs. FCCM 2013: 89-96 - [c54]Jason Helge Anderson, Stephen Dean Brown, Andrew Canis, Jongsok Choi:
High-level synthesis with LegUp: a crash course for users and researchers. FPGA 2013: 7-8 - [c53]Jongsok Choi, Stephen Dean Brown, Jason Helge Anderson:
From software threads to parallel hardware in high-level synthesis for FPGAs. FPT 2013: 270-277 - [c52]Jiu Cheng Cai, Ruolong Lian, Mengyao Wang, Andrew Canis, Jongsok Choi, Blair Fort, Eric Hart, Emily Miao, Yanyan Zhang, Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson:
From C to Blokus Duo with LegUp high-level synthesis. FPT 2013: 486-489 - 2012
- [c51]Jongsok Choi, Kevin Nam, Andrew Canis, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski:
Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems. FCCM 2012: 17-24 - [c50]Stefan Hadjis, Andrew Canis, Jason Helge Anderson, Jongsok Choi, Kevin Nam, Stephen Dean Brown, Tomasz S. Czajkowski:
Impact of FPGA architecture on resource sharing in high-level synthesis. FPGA 2012: 111-114 - 2011
- [j15]Andrew C. Ling, Stephen Dean Brown, Sean Safarpour, Jianwen Zhu:
Toward Automated ECOs in FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(1): 18-30 (2011) - [c49]Mark Aldham, Jason Helge Anderson, Stephen Dean Brown, Andrew Canis:
Low-cost hardware profiling of run-time and energy in FPGA embedded processors. ASAP 2011: 61-68 - [c48]Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski:
LegUp: high-level synthesis for FPGA-based processor/accelerator systems. FPGA 2011: 33-36 - 2010
- [j14]Tomasz S. Czajkowski, Stephen Dean Brown:
Decomposition-Based Vectorless Toggle Rate Computation for FPGA Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1723-1735 (2010)
2000 – 2009
- 2009
- [c47]Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour:
Towards automated ECOs in FPGAs. FPGA 2009: 3-12 - [c46]Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown:
Enhancements to FPGA design methodology using streaming. FPL 2009: 294-301 - 2008
- [j13]Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown:
Scalable Synthesis and Clustering Techniques Using Decision Diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3): 423-435 (2008) - [j12]Tomasz S. Czajkowski, Stephen Dean Brown:
Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2236-2249 (2008) - [c45]Tomasz S. Czajkowski, Stephen Dean Brown:
Functionally linear decomposition and synthesis of logic circuits for FPGAs. DAC 2008: 18-23 - [c44]Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown:
Towards Compilation of Streaming Programs into FPGA Hardware. FDL 2008: 67-72 - [c43]Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown:
Stream Programming for FPGAs. FDL (Selected Papers) 2008: 241-253 - [c42]Tomasz S. Czajkowski, Stephen Dean Brown:
Fast toggle rate computation for FPGA circuits. FPL 2008: 65-70 - [c41]Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown:
Delay driven AIG restructuring using slack budget management. ACM Great Lakes Symposium on VLSI 2008: 163-166 - 2007
- [j11]Deshanand P. Singh, Stephen Dean Brown:
An area-efficient timing closure technique for FPGAs using Shannon's expansion. Integr. 40(2): 167-173 (2007) - [j10]Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown:
FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1196-1210 (2007) - [j9]Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown:
Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. IEEE Trans. Very Large Scale Integr. Syst. 15(8): 895-903 (2007) - [c40]Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown:
BddCut: Towards Scalable Symbolic Cut Enumeration. ASP-DAC 2007: 408-413 - [c39]Tomasz S. Czajkowski, Stephen Dean Brown:
Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits. DAC 2007: 324-329 - [c38]Franjo Plavec, Zvonko G. Vranesic, Stephen Dean Brown:
On Digital Search Trees - A Simple Method for Constructing Balanced Binary Trees. ICSOFT (PL/DPS/KE/MUSE) 2007: 61-68 - [c37]Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown:
Incremental placement for structured ASICs using the transportation problem. VLSI-SoC 2007: 172-177 - 2006
- [j8]Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic:
Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2331-2340 (2006) - [c36]Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown:
A Multithreaded Soft Processor for SoPC Area Reduction. FCCM 2006: 131-142 - [c35]Mehrdad Eslami Dehkordi, Stephen Dean Brown, Terry P. Borer:
Modular Partitioning for Incremental Compilation. FPL 2006: 1-6 - [c34]Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic:
Adaptive FPGAs: High-Level Architecture and a Synthesis Method. FPL 2006: 1-8 - [c33]Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown:
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. ICCAD 2006: 135-142 - [c32]Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown:
Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. SLIP 2006: 3-8 - 2005
- [c31]Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown:
Two-stage physical synthesis for FPGAs. CICC 2005: 171-178 - [c30]Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown:
FPGA technology mapping: a study of optimality. DAC 2005: 427-432 - [c29]Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown:
Incremental retiming for FPGA physical synthesis. DAC 2005: 433-438 - [c28]Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown:
FPGA PLB Evaluation using Quantified Boolean Satisfiability. FPL 2005: 19-24 - [c27]Valavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown:
Post-Placement BDD-Based Decomposition for FPGAs. FPL 2005: 31-38 - [c26]Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen Dean Brown:
Experiences with Soft-Core Processor Design. IPDPS 2005 - [c25]Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown:
FPGA Logic Synthesis Using Quantified Boolean Satisfiability. SAT 2005: 444-450 - 2004
- [c24]Shawn Malhotra, Terry P. Borer, Deshanand P. Singh, Stephen Dean Brown:
The Quartus University Interface Program: enabling advanced FPGA research. FPT 2004: 225-230 - [c23]Mehrdad Eslami Dehkordi, Stephen Dean Brown:
Retiming aware clustering for sequential circuits. FPT 2004: 391-394 - 2003
- [c22]Mehrdad Eslami Dehkordi, Stephen Dean Brown:
Recursive circuit clustering for minimum delay and area. FPGA 2003: 242 - [c21]Mehrdad Eslami Dehkordi, Stephen Dean Brown:
Performance-driven recursive multi-level clustering. FPT 2003: 262-269 - [c20]Deshanand P. Singh, Terry P. Borer, Stephen Dean Brown:
Automated Extraction of Physical Hierarchies for Performance Improvement on Programmable Logic Devices. VLSI 2003: 28-33 - [c19]Deshanand P. Singh, Stephen Dean Brown:
An Area-Efficient Timing Closure Technique for FPGAs Using Shannon's Expansion. VLSI 2003: 41-50 - [c18]Zvonko G. Vranesic, Stephen Dean Brown:
Use of HDLs in teaching of computer hardware courses. WCAE 2003: 16 - 2002
- [c17]Deshanand P. Singh, Stephen Dean Brown:
Integrated retiming and placement for field programmable gate arrays. FPGA 2002: 67-76 - [c16]Deshanand P. Singh, Stephen Dean Brown:
Constrained clock shifting for field programmable gate arrays. FPGA 2002: 121-126 - [c15]Valavan Manohararajah, Terry P. Borer, Stephen Dean Brown, Zvonko G. Vranesic:
Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. FPL 2002: 232-241 - [c14]Mehrdad Eslami Dehkordi, Stephen Dean Brown:
The effect of cluster packing and node duplication control in delay driven clustering. FPT 2002: 227-233 - [c13]Deshanand P. Singh, Stephen Dean Brown:
Incremental placement for layout driven optimizations on FPGAs. ICCAD 2002: 752-759 - 2001
- [c12]Deshanand P. Singh, Stephen Dean Brown:
The case for registered routing switches in field programmable gate arrays. FPGA 2001: 161-169 - 2000
- [c11]Alireza Kaviani, Stephen Dean Brown:
Technology mapping issues for an FPGA with lookup tables and PLA-like blocks. FPGA 2000: 60-66 - [c10]R. Grindley, Tarek S. Abdelrahman, Stephen Dean Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic:
The NUMAchine Multiprocessor. ICPP 2000: 487-496
1990 – 1999
- 1999
- [j7]Alireza Kaviani, Stephen Dean Brown:
The Hybrid Field-Programmable Architecture. IEEE Des. Test Comput. 16(2): 74-83 (1999) - 1998
- [c9]Alireza Kaviani, Daniel Vranesic, Stephen Dean Brown:
Computational field programmable architecture. CICC 1998: 261-264 - [c8]A. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic:
Design and Implementation of the NUMAchine Multiprocessor. DAC 1998: 66-69 - [c7]Jason Helge Anderson, Stephen Dean Brown:
Technology Mapping for Large Complex PLDs. DAC 1998: 698-703 - [c6]Jason Helge Anderson, Stephen Dean Brown:
An LPGA with Foldable PLA-style Logic Blocks. FPGA 1998: 244-252 - 1997
- [c5]Guy G. Lemieux, Stephen Dean Brown, Daniel Vranesic:
On two-step routing for FPGAS. ISPD 1997: 60-66 - 1996
- [j6]Stephen Dean Brown, Jonathan Rose:
FPGA and CPLD Architectures: A Tutorial. IEEE Des. Test Comput. 13(2): 42-57 (1996) - [j5]Stephen Dean Brown:
FPGA Architectural Research: A Survey. IEEE Des. Test Comput. 13(4): 9-15 (1996) - [j4]Stephen Dean Brown, Muhammad M. Khellah, Zvonko G. Vranesic:
Minimizing FPGA Interconnect Delays. IEEE Des. Test Comput. 13(4): 16-23 (1996) - [j3]Stephen Dean Brown, Muhammad M. Khellah, Guy Lemieux:
Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays. VLSI Design 4(4): 275-291 (1996) - [c4]Stephen Dean Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic:
Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools. DAC 1996: 427-432 - [c3]Alireza Kaviani, Stephen Dean Brown:
Hybrid FPGA Architecture. FPGA 1996: 3-9 - 1993
- [j2]Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic:
A stochastic model to predict the routability of field-programmable gate arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(12): 1827-1838 (1993) - 1992
- [j1]Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic:
A detailed router for field-programmable gate arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(5): 620-628 (1992) - [c2]Benjamin Tseng, Jonathan Rose, Stephen Dean Brown:
Improving FPGA Routing Architectures Using Architecture and CAD Interactions. ICCD 1992: 99-104 - 1990
- [c1]Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic:
A Detailed Router for Field-Programmable Gate Arrays. ICCAD 1990: 382-385
Coauthor Index
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