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ORCIDSoC 2004, Tampere, Finland
- Proceedings of the 2004 International Symposium on System-on-Chip, Tampere, Finland, November 16-18, 2004. IEEE 2004, ISBN 0-7803-8558-6
- Ramchan Woo:
3D graphics circuits for 3G multimedia terminals. - Stefan Rusu:
Clock generation and distribution in high-performance processors. - Franz Dielacher
:
SoC-Mobinet: broadband transceiver design challenges. - Chun-Yen Chang:
Development of NSoC program in Taiwan. - Tero Rissa, Wayne Luk:
Reduction of design complexity using virtual hardware platforms. - Marcello Coppola, Riccardo Locatelli, Giuseppe Maruccia, Lorenzo Pieralisi, Alberto Scandurra:
Spidergon: a novel on-chip communication network. - Mattan Erez:
Stream architectures - efficiency and programmability. - Paul Metzgen:
Optimizing a high performance 32-bit processor for programmable logic. - Heinrich Meyr:
Application specific instruction-set processors (ASIP's) for wireless communications: design, cost, and energy efficiency vs. flexibility. 1-2 - Stefano Angioni, Floyd Lazare:
Implementing a single-processor cellular modem on an SC1000-family core. 3-7 - Yong Luo, Anatoly Moskalev, Laurence E. Bays, Brian J. Petryna:
A high linearity analog front end for multiprocessor SOC integration. 9-12 - Jian Liu, Li-Rong Zheng, Hannu Tenhunen:
Global routing for multicast-supporting TDM network-on-chip. 17-20 - Zhonghai Lu, Axel Jantsch:
Flit admission in on-chip wormhole-switched networks with virtual channels. 21-24 - Sumant Sathe, Daniel Wiklund, Dake Liu:
Design of a guaranteed throughput router for on-chip networks. 25-28 - Gerard J. M. Smit, Paul M. Heysters, Michèl A. J. Rosien, Bert Molenkamp:
Lessons learned from designing the MONTIUM - a coarse-grained reconfigurable processing tile. 29-32 - Martti Forsell:
Efficient barrier synchronization mechanism for emulated shared memory NOCs. 33-36 - Mehmet Derin Harmanci, Nuria Pazos Escudero, Yusuf Leblebici, Paolo Ienne:
Providing QoS to connection-less packet-switched NoC by implementing DiffServ functionalities. 37-40 - Jari Kreku, Tarja Kauppi, Juha-Pekka Soininen:
Evaluation of platform architecture performance using abstract instruction-level workload models. 43-48 - Jouni Riihimäki, Petri Kukkala, Erno Salminen, Marko Hännikäinen, Kimmo Kuusilinna, Timo D. Hämäläinen:
Practical distributed simulation of a network of wireless terminals. 49-52 - Cade C. Wells, Ed Duncan, David Renshaw:
A model for imaging system-on-chip manufacturing costs. 53-56 - Shaojun Wu:
A low-noise fast-settling PLL frequency synthesizer for CDMA receivers. 57-60 - Koji Inoue, Hidekazu Tanaka, Vasily G. Moshnyaga, Kazuaki J. Murakami:
A low-power I-cache design with tag-comparison reuse. 61-67 - Erno Salminen, Kimmo Kuusilinna, Timo D. Hämäläinen:
Comparison of hardware IP components for system-on-chip. 69-73 - Erwin Ofner, Jari Nurmi, Jan Madsen, Jouni Isoaho, Hannu Tenhunen:
SoC-Mobinet, R&D and education in system-on-chip design. 77-80 - Kashif Virk, Jan Madsen:
A system-level multiprocessor system-on-chip modeling framework. 81-84 - Christian Panis, Ulrich Hirnschrott, Stefan Farfeleder, Andreas Krall, Gunther Laure, Wolfgang Lazian, Jari Nurmi:
A scalable embedded DSP core for SoC applications. 85-88 - Ethiopia Nigussie, Johanna Tuominen, Jouni Isoaho:
Analyses of signaling techniques for self-timed systems. 89-92 - Heikki Kariniemi, Jari Nurmi:
Reusable XGFT interconnect IP for network-on-chip implementations. 95-102 - Claudio Brunelli, Fabio Campi, Juha Kylliäinen, Jari Nurmi:
A reconfigurable FPU as IP component for SoCs. 103-106 - Tuukka Kasanko, Jari Nurmi:
Verification of a 32-bit RISC processor core. 107-110 - Alfred Blaickner, Susanne Albl, Wolfgang Scherr:
Configurable computing architectures for wireless and software defined radio - a FPGA prototyping experience using high level design-tool-chains. 111-116 - Tapio Ristimäki, Jari Nurmi:
Reconfigurable IP blocks: a survey [SoC]. 117-122 - Xin Wang, Tapani Ahonen, Jari Nurmi:
A synthesizable RTL design of asynchronous FIFO. 123-128 - Tapani Ahonen, Jari Nurmi:
Design reuse and design for reuse, a case study on HDSL2. 129-133 - David A. Sigüenza-Tortosa, Jari Nurmi:
Topology design for global link optimization in application specific network-on-chips. 135-138 - Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen:
Crosstalk immune interconnect driver design. 139-142 - Timo Rintakoski, Mika Kuulusa, Jari Nurmi:
Hardware unit for OVSF/Walsh/Hadamard code generation [3G mobile communication applications]. 143-145 - Jacob Bower:
A system-on-a-chip for audio encoding. 149-155 - Martti Forsell:
Ec - a compiler for the e-language [NOC applications]. 157-160 - H. J. Kadim:
Estimation of a maximum bound of uncertain parameter fluctuations with applications to analogue IP-cores. 161-164 - Iosif Antochi, Bernardus Juurlink, Stamatis Vassiliadis, Petri Liuha:
Efficient tile-aware bounding-box overlap test for tile-based rendering. 165-168 - Shinichiro Gomi, Kohichi Nakamura, Hiroyuki Ito, Hideyuki Sugita, Kenichi Okada, Kazuya Masu:
High speed and low power on-chip micro network circuit with differential transmission line. 173-176 - Ali Habibi, Amjad Gawanmeh, Sofiène Tahar:
Assertion based verification of PSL for SystemC designs. 177-180 - Chinhung Chan, Yucheng Chang, Hsichi Ho, Herming Chiueh:
A thermal-aware power management soft-IP for platform-based SoC designs. 181-184 - Arkadiy Morgenshtein, Israel Cidon, Avinoam Kolodny, Ran Ginosar:
Comparative analysis of serial vs parallel links in NoC. 185-188 - Goran Andrijevic, Håkan Magnusson, Håkan K. Olsson:
A fully integrated low-IF DVB-T receiver architecture. 189-192 - R. Pelliconi, Fabio Campi, L. Salsa, Claudio Mucci, S. Macchiavelli:
An in-circuit debug environment for multiprocessor SOCs based on a HDL RISC soft-core. 193-196 - Juha Plosila, Pasi Liljeberg, Jouni Isoaho:
Refinement of on-chip communication channels. 197-200 - Karim Oumalou, Ali Habibi, Sofiène Tahar:
Design for verification of a PCI bus in SystemC. 201-204
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