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ORCIDSoC 2011: Tampere, Finland
- 2011 International Symposium on System on Chip, SoC 2011, Tampere, Finland, October 31 - November 2, 2011. IEEE 2011, ISBN 978-1-4577-0671-4
- Subayal Khan, Jukka Saastamoinen, Mikko Majanen, Jyrki Huusko
, Jari Nurmi:
Analyzing transport and MAC layer in system-level performance simulation. 1-8 - Milos Krstic, Xin Fan, Eckhard Grass, Christoph Heer, Birgit Sanders, Luca Benini, Mohammad Reza Kakoee, Alessandro Strano, Davide Bertozzi:
Moonrake chip - GALS demonstrator in 40 nm CMOS technology. 9-13 - Firew Siyoum, Marc Geilen, Orlando Moreira, Rick J. M. Nas, Henk Corporaal:
Analyzing synchronous dataflow scenarios for dynamic software-defined radio applications. 14-21 - Tomoki Ikegaya, Ryosuke Oda, Tatsuhiro Yamada, Tomoaki Tsumura, Hiroshi Matsuo, Yasuhiko Nakashima:
A hybrid model of speculative execution and scout threading for auto-memoization processor. 22-28 - Pekka Jääskeläinen, Erno Salminen, Otto Esko, Jarmo Takala:
Customizable Datapath Integrated Lock Unit. 29-33 - Daniele Bortolotti, Francesco Paterna, Christian Pinto, Andrea Marongiu, Martino Ruggiero, Luca Benini:
Exploring instruction caching strategies for tightly-coupled shared-memory clusters. 34-41 - Mikhail J. Moiseev, Alexey V. Zakharov, Ilya Klotchkov, Sergey I. Salishev:
Static analysis method for deadlock detection in SystemC designs. 42-47 - Zubair Wadood Bhatti, Davy Preuveneers, Yolande Berbers, Narasinga Rao Miniskar, Roel Wuyts:
SAMOSA: Scratchpad aware mapping of streaming applications. 48-55 - Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Jean-Luc Dekeyser:
A system level power consumption estimation for MPSoC. 56-61 - Claudio Brunelli, Eero Aho, Heikki Berg:
OpenCL implementation of Cholesky matrix decomposition. 62-67 - Mehdi Modarressi, Seyed Hossein Nikounia, Amir Hossein Jahangir:
Low-power arithmetic unit for DSP applications. 68-71 - Issam W. Damaj:
Co-designs of parallel Rijndael. 72-77 - Esko Pekkarinen, Lasse Lehtonen, Erno Salminen, Timo D. Hämäläinen:
A set of traffic models for Network-on-Chip benchmarking. 78-81 - Vladimír Guzma, Teemu Pitkänen, Jarmo Takala:
Effects of loop unrolling and use of instruction buffer on processor energy consumption. 82-85 - Erno Salminen, Timo D. Hämäläinen, Marko Hännikäinen:
Applying IP-XACT in product data management. 86-91 - Christoph Schmutzler, Abdallah Lakhtel, Martin Simons, Jürgen Becker:
Increasing energy efficiency of automotive E/E-architectures with Intelligent Communication Controllers for FlexRay. 92-95 - Uli Kretzschmar, Armando Astarloa, Jesús Lázaro, Jaime Jimenez, Aitzol Zuloaga:
An automatic experimental set-up for robustness analysis of designs implemented on SRAM FPGAS. 96-101 - Mohammad Badawi, Ahmed Hemani:
A coarse-grained reconfigurable protocol processor. 102-107 - Teodor Tite, Adelina Vig, Nicolae Olteanu, Cristian Cuna:
moviTest: A Test Environment dedicated to multi-core embedded architectures. 108-111 - Sebastian Höppner, Dennis Walter, Georg Ellguth, René Schüffny:
Mismatch characterization of high-speed NoC links using asynchronous sub-sampling. 112-115 - Tim Wegner, Martin Gag, Dirk Timmermann:
Impact of proactive temperature management on performance of Networks-on-Chip. 116-121 - Marco Ferraresi, Giuseppina Gobbo, Daniele Ludovici, Davide Bertozzi:
Bringing Network-on-Chip links to 45nm. 122-127 - Omer Malik, Ahmed Hemani:
Synchronizing distributed state machines in a coarse grain reconfigurable architecture. 128-135 - Weihua Sheng, Stefan Schürmans, Maximilian Odendahl, Rainer Leupers, Gerd Ascheid:
Automatic calibration of streaming applications for software mapping exploration. 136-142 - Yaset Oliva, Maxime Pelcat, Jean-François Nezan, Jean-Christophe Prévotet, Slaheddine Aridhi:
Building a RTOS for MPSoC dataflow programming. 143-146
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