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ORCIDISSoC 2014: Tampere, Finland
- Jari Nurmi, Peeter Ellervee, Dragomir Milojevic, Ondrej Daniel, Tommi Paakki:
2014 International Symposium on System-on-Chip, SoC 2014, Tampere, Finland, October 28-29, 2014. IEEE 2014, ISBN 978-1-4799-6890-9 - Daniel Günther, Andreas Bytyn, Rainer Leupers, Gerd Ascheid:
Energy-efficiency of floating-point and fixed-point SIMD cores for MIMO processing systems. 1-7 - Christoforos Kachris, Georgios Ch. Sirakoulis
, Dimitrios Soudris:
A Reconfigurable MapReduce accelerator for multi-core all-programmable SoCs. 1-6 - Matteo Cuppini, Eleonora Franchi Scarselli, Claudio Mucci, Roberto Canegallo:
Soft-core eFPGA for Smart Power applications. 1-4 - Daniel Gregorek, Alberto García Ortiz:
A transaction-level framework for design-space exploration of hardware-enhanced operating systems. 1-4 - Elena Dubrova, Mats Näslund, Gunnar Carlsson, Ben J. M. Smeets:
Keyed logic BIST for Trojan detection in SoC. 1-4 - Janne Virtanen, Lauri Matilainen, Erno Salminen, Timo D. Hämäläinen:
Implementation of Multicore communications API. 1-6 - Yuuki Shibata, Takanori Tsumura, Tomoaki Tsumura, Yasuhiko Nakashima:
An implementation of Auto-Memoization mechanism on ARM-based superscalar processor. 1-8 - Wayne Kelly, Martin Flasskamp, Gregor Sievers, Johannes Ax, Jianing Chen, Christian Klarhorst, Christoph Ragg, Thorsten Jungeblut, Andrew Sorensen:
A communication model and partitioning algorithm for streaming applications for an embedded MPSoC. 1-6 - Michael Meixner, Tobias G. Noll:
Limits of gate-level power estimation considering real delay effects and glitches. 1-7 - Kimiyoshi Usami, Makoto Miyauchi, Masaru Kudo, Kazumitsu Takagi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. 1-7 - Oliver Arnold, Felix Neumaerker, Gerhard P. Fettweis:
L2_ISA++: Instruction set architecture extensions for 4G and LTE-advanced MPSoCs. 1-8 - Jan Moritz Joseph, Thilo Pionteck:
A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling. 1-6 - Timo D. Hämäläinen, Erno Salminen:
Gamification of System-on-Chip design. 1-8 - Mikko Honkonen, Lauri Matilainen, Erno Salminen, Timo D. Hämäläinen:
WOKE: A novel workflow model editor. 1-8 - Alex Schönberger, Klaus Hofmann:
Fast Memory Region: 3D DRAM memory concept evaluated for JPEG2000 algorithm. 1-4 - Oliver Arnold, Gerhard P. Fettweis:
Adaptive runtime management of heterogenous MPSoCs: Analysis, acceleration and silicon prototype. 1-4 - Jirí Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický:
System on chip design of a linear system solver. 1-6 - Philipp Wehner, Diana Göhringer:
Parallel and distributed simulation of networked multi-core systems. 1-5 - Martin Broich, Tobias G. Noll:
Optimal data path widths for energy- and area-efficient Max-Log-MAP based LTE Turbo decoders. 1-8 - George Kornaros, Konstantinos Harteros, Ioannis Christoforakis, Maria Astrinaki:
I/O virtualization utilizing an efficient hardware system-level Memory Management Unit. 1-4 - Anam Zaman, Osman Hasan:
Formal verification of circuit-switched Network on chip (NoC) architectures using SPIN. 1-8 - Feriel Ben Abdallah, Chiraz Trabelsi, Rabie Ben Atitallah, Mourad Abed:
Early power-aware Design Space Exploration for embedded systems: MPEG-2 case study. 1-8 - Waqar Hussain, Henry Hoffmann, Tapani Ahonen, Jari Nurmi:
Constraint-driven frequency scaling in a Coarse Grain Reconfigurable Array. 1-6 - Pei Liu, Ahmed Hemani, Kolin Paul:
A many-core hardware acceleration platform for short read mapping problem using distributed memory interface with 3D-stacked architecture. 1-8
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