default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID12th MCSoC 2018: Hanoi, Vietnam
- 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2018, Hanoi, Vietnam, September 12-14, 2018. IEEE Computer Society 2018, ISBN 978-1-5386-6689-0
Session 1: Multicore/Manycore SoCs Architectures and Programming
- Elishai Ezra Tsur
, Elyassaf Madar, Natan Danan:
Code Generation of Graph-Based Vision Processing for Multiple CUDA Cores SoC Jetson TX. 1-7 - Yosi Ben-Asher, Vladislav Tartakovsky, Katrina Portman, Orr Zilberman, Avishi Hadar:
An FPGA Scalable Parallel Viterbi Decoder. 8-15 - Yuuma Azuma, Hayato Sakagami, Kenji Kise:
An Efficient Parallel Hardware Scheme for Solving the N-Queens Problem. 16-22 - Shunsuke Mie, Yuichi Okuyama, Hiroaki Saito:
Simplified Quadcopter Simulation Model for Spike-Based Hardware PID Controller using SystemC-AMS. 23-27
Session 2: Multicore/Manycore SoCs Design
- Yosi Ben-Asher, Irina Lipov:
Unifying Wire and Time Scheduling for Highlevel Synthesis. 28-35 - Khoa Dang Pham, Edson L. Horta, Dirk Koch, Anuj Vaishnav, Thomas Kuhn:
IPRDF: An Isolated Partial Reconfiguration Design Flow for Xilinx FPGAs. 36-43 - Ghazanfar Ali, Jerrin Pathrose, Hans G. Kerkhoff:
On-Chip Lifetime Prediction for Dependable Many-Processor SoCs Based on Data Fusion. 44-51 - Aleksandr Kostrov, Viktor Stempitsky, Artur Borovik, Vladimir Tchekhovsky:
Design Features of Analog-to-Digital Solutions for the Tracking Detector Readout Electronics. 52-56
Session 3: Special Session on Artificial Intelligence for Multimedia Communications
- Son Ngoc Duong, Anh Vu-Tuan Trinh, Thai-Mai Dinh:
Bluetooth Low Energy Based Indoor Positioning on iOS Platform. 57-63 - Thao Nguyen Thi Huong, Huy Phi Cong, Xiem HoangVan, Tien Huu Vu:
A Practical High Efficiency Video Coding Solution for Visual Sensor Network using Raspberry Pi Platform. 64-68 - Xiem HoangVan, Le Dao Thi Hue, Giap PhamVan:
Adaptive Long-Term Reference Selection for Efficient Scalable Surveillance Video Coding. 69-73 - Vinh Van Duong, Thuong Nguyen Canh, Byeungwoo Jeon:
Light Field Image Coding for Efficient Refocusing. 74-78
Session 4: Special Session on Intelligent Systems and Learning Technologies: Models, Methods, and Applications
- Mohamed Hamada, Abdulsalam Latifat, Mohammed Hassan:
Adaptive Genetic Algorithm for Improving Prediction Accuracy of a Multi-Criteria Recommender System. 79-86 - Mohamed Hamada, Nkiruka Bridget Odu, Mohammed Hassan:
A Fuzzy-Based Approach for Modelling Preferences of Users in Multi-Criteria Recommender Systems. 87-94
Session 5: Embedded and Real-Time Multicore/Manycore SoC Systems
- Phuc-Vinh Nguyen, Thi-Thu-Trang Tran, Phuoc-Loc Diep, Duc-Hung Le:
A Low-Power ASIC Implementation of Multi-Core OpenSPARC T1 Processor on 90nm CMOS Process. 95-100 - Doan Duy, Kiyofumi Tanaka:
A Novel Task-to-Processor Assignment Approach for Optimal Multiprocessor Real-Time Scheduling. 101-108 - Hidehito Yabuuchi, Shinichi Awamoto, Hiroyuki Chishiro, Shinpei Kato:
Multikernel Design and Implementation for Improving Responsiveness of Aperiodic Tasks. 109-116
Session 6: Special Session on Auto-Tuning for Multicore and GPU (ATMG2018)
- Kazuhiko Komatsu, Takumi Kishitani, Masayuki Sato, Akihiro Musa, Hiroaki Kobayashi:
Search Space Reduction for Parameter Tuning of a Tsunami Simulation on the Intel Knights Landing Processor. 117-124 - Masatoshi Takayanagi, Tomohiro Suzuki:
Communication-Avoiding Tile QR Decomposition on CPU/GPU Heterogeneous Cluster System. 125-131 - Hyeongyun Moon, Jeonghun Cho, Daejin Park:
Freeze-Safe IoT Hibernation using Power Profile Monitor Based on Communication-Centric Auto-Tuning. 132-137
Session 7: Multicore/Manycore Interconnection Networks
- Leonard Masing, Akshay Srivatsa, Fabian Kreß, Nidhi Anantharajaiah, Andreas Herkersdorf, Jürgen Becker:
In-NoC Circuits for Low-Latency Cache Coherence in Distributed Shared-Memory Architectures. 138-145 - Akram Ben Ahmed, Hayate Okuhara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip Systems. 146-153 - Khanh N. Dang, Xuan-Tu Tran:
Parity-Based ECC and Mechanism for Detecting and Correcting Soft Errors in On-Chip Communication. 154-161 - Hiliwi Leake Kidane, El-Bay Bourennane:
MARTE and IP-XACT Based Approach for Run-Time Scalable NoC. 162-167
Session 8: Special Session on Scalable and Flexible Many-Core Mapping Techniques
- Vanchinathan Venkataramani, Anuj Pathania, Muhammad Shafique, Tulika Mitra, Jörg Henkel:
Scalable Dynamic Task Scheduling on Adaptive Many-Core. 168-175 - Tobias Schwarzer, Sascha Roloff, Valentina Richthammer, Rami Khaldi, Stefan Wildermann, Michael Glaß, Jürgen Teich:
On the Complexity of Mapping Feasibility in Many-Core Architectures. 176-183 - Andres Goens, Christian Menard, Jerónimo Castrillón:
On the Representation of Mappings to Multicores. 184-191
Session 9: Multicore/Manycore SoCs Applications
- Moisés Urbina, Roman Obermaisser:
Evaluation of Performance and Fault Containment in AUTOSAR Micro-ECUs on a Multi-Core Processor. 192-200 - Elsayed A. Elsayed, Kenji Kise:
Design and Evaluation of a Configurable Hardware Merge Sorter for Various Output Records. 201-208 - Incheon Paik, Yuji Ishizuka, Quang-Minh Do, Wuhui Chen:
On-Line Cost-Aware Workflow Allocation in Heterogeneous Computing Environments. 209-216 - Kenji Kanazawa, Shaowei Cai:
FPGA Acceleration to Solve Maximum Clique Problems Encoded into Partial MaxSAT. 217-224
Session 10: Algorithms and Hardware for Learning On-Chip and Embedded Neuromorphic Computing Systems
- Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham:
VLSI Design of Floating-Point Twiddle Factor Using Adaptive CORDIC on Various Iteration Limitations. 225-232 - Van-Tinh Nguyen, Tieu-Khanh Luong, Han Le Duc, Van-Phuc Hoang:
An Efficient Hardware Implementation of Activation Functions Using Stochastic Computing for Deep Neural Networks. 233-236 - Takumi Kudo, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Ryota Uematsu, Yuka Oba, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki:
Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators. 237-243 - Mohammad Loni, Amin Majd, Abdolah Loni, Masoud Daneshtalab, Mikael Sjödin, Elena Troubitsyna:
Designing Compact Convolutional Neural Network for Embedded Stereo Vision Systems. 244-251
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-04 22:07 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
