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ORCID26th PATMOS 2016: Bremen, Germany
- 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016, Bremen, Germany, September 21-23, 2016. IEEE 2016, ISBN 978-1-5090-0733-2
- Malgorzata Michalska, J. J. Ahmad, Endri Bezati, Simone Casale Brunet, Marco Mattavelli:
Performance estimation of program partitions on multi-core platforms. 1-8 - Teng Xu, Miodrag Potkonjak:
Pipelining for dual supply voltages. 9-16 - Matthew J. Walker
, Stephan Diestelhorst, Andreas Hansson, Domenico Balsamo, Geoff V. Merrett, Bashir M. Al-Hashimi:
Thermally-aware composite run-time CPU power models. 17-24 - Aida Todri-Sanial:
Investigation of electrical and thermal properties of carbon nanotube interconnects. 25-32 - Toufik Sadi, Liping Wang, Asen Asenov:
Multi-scale electrothermal simulation and modelling of resistive random access memory devices. 33-37 - Philippe Dollfus, V. Hung Nguyen, V. Truong Tran, M. Chung Nguyen, Arnaud Bournel, Jerome Saint-Martin:
Thermoelectric effects in graphene and graphene-based nanostructures using atomistic simulation. 38-43 - Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera:
Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing. 44-49 - Mohammad Saber Golanbari, Saman Kiamehr, Mehdi Baradaran Tahoori:
Hold-time violation analysis and fixing in near-threshold region. 50-55 - James Myers, Pranay Prabhat, Anand Savanth, Sheng Yang, Rohan Gaddh:
Design challenges for near and sub-threshold operation: A case study with an ARM Cortex-M0+ based WSN subsystem. 56-63 - Ioannis S. Stamelakos, Sotirios Xydis, Gianluca Palermo, Cristina Silvano:
Throughput balancing for energy efficient near-threshold manycores. 64-69 - Thomas Noulis:
CMOS process transient noise simulation analysis and benchmarking. 70-75 - Erica Tena-Sánchez, Antonio J. Acosta, Juan Núñez:
Secure cryptographic hardware implementation issues for high-performance applications. 76-83 - Jia Guo, Miodrag Potkonjak:
Coarse-grained learning-based dynamic voltage frequency scaling for video decoding. 84-91 - Muhammad Adeel Tajammul, Syed M. A. H. Jafri, Ahmed Hemani, Peeter Ellervee:
TransMem: A memory architecture to support dynamic remapping and parallelism in low power high performance CGRAs. 92-99 - Roman Kaplan, Leonid Yavits, Amir Morad, Ran Ginosar:
Deduplication in resistive content addressable memory based solid state drive. 100-106 - Jorge L. Tonfat, Guilherme Flach, Ricardo Reis:
Leakage current analysis in static CMOS logic gates for a transistor network design approach. 107-113 - Parham Haririan, Alberto García Ortiz:
Run-time schedulability check of real-time tasks for energy efficiency. 114-119 - Hossein Aghababa, Mohammadreza Kolahdouz, Behjat Forouzandeh:
Analysis of stress effects on timing of nano-scaled CMOS digital integrated circuits. 120-127 - Luca Larcher, Francesco Maria Puglisi, Andrea Padovani, Luca Vandelli, Paolo Pavan:
Multiscale modeling of electron-ion interactions for engineering novel electronic devices and materials. 128-132 - Sebastian Volz, Haoxue Han:
Optimized few layer graphene for heat spreading. 133-135 - Theodor Hillebrand, Timur Schafer, Nico Hellwege, Marco Erstling, Dagmar Peters-Drolshagen, Steffen Paul:
Design and verification of analog CMOS circuits using the gm/ID-method with age-dependent degradation effects. 136-141 - Peyman Pouyan, Esteve Amat, Said Hamdioui, Antonio Rubio:
RRAM variability and its mitigation schemes. 141-146 - Georgia Psychou, Tobias Gemmeke, Tobias G. Noll:
A framework for analyzing the propagation of hardware-induced errors in non-recursive LTI blocks with finite wordlength effects. 147-154 - Stephanie O. Ames, Vinicius Zanandrea, Ingrid F. V. Oliveira, Samuel P. Toledo, Cristina Meinhardt:
Investigating PVT variability effects on full adders. 155-161 - Pierre-Yves Peneau, Rabab Bouziane, Abdoulaye Gamatié, Erven Rohou, Florent Bruguier, Gilles Sassatelli, Lionel Torres, Sophiane Senni:
Loop optimization in presence of STT-MRAM caches: A study of performance-energy tradeoffs. 162-169 - Jason Xin Zheng, Teng Xu, Miodrag Potkonjak:
Securing embedded systems and their IPs with digital reconfigurable PUFs. 169-176 - Himadri Singh Raghav, Vivian A. Bartlett, Izzet Kale:
Energy efficiency of 2-step charging power-clock for adiabatic logic. 176-182 - Alireza Rohani, Hassan Ebrahimi, Hans G. Kerkhoff:
A software framework to calculate local temperatures in CMOS processors. 183-188 - Ahmad N. Abdulfattah, Charalampos C. Tsimenidis, Alex Yakovlev:
Subthreshold-based m-sequence code generator for ultra low-power body sensor nodes. 189-195 - Xiaohan Yang, Adedotun Adeyemo, Anu Bala, Abusaleh M. Jabir:
Novel memristive logic architectures. 196-199 - Radi Husin Bin Ramlee, Mark Zwolinski:
Using Iddt current degradation to monitor ageing in CMOS circuits. 200-204 - Dominik Macko:
PMHLS 2.0: An automated optimization of power management during high-level synthesis. 205-212 - Jia Guo, Teng Xu, Theano Stavrinos, Miodrag Potkonjak:
Enabling environmentally-powered indoor sensor networks with dynamic routing and operation. 213-220 - Vojtech Mrazek, Zdenek Vasícek:
Automatic design of arbitrary-size approximate sorting networks with error guarantee. 221-228 - Thiago Ferreira de Paiva Leite, Rodrigo Possamai Bastos, Rodrigo Iga Jadue, Laurent Fesquet:
Comparison of low-voltage scaling in synchronous and asynchronous FD-SOI circuits. 229-234 - Yahia Benmoussa, Eric Senn, Nicolas Derouineau, Nicolas Tizon, Jalil Boukhobza:
Green metadata based adaptive DVFS for energy efficient video decoding. 235-242 - Francisco Veirano, Lirida A. B. Naviner, Fernando Silveira:
Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI. 243-249 - Jie Liang, Liuyang Zhang, Nadine Azémard-Crestani, Pascal Nouet, Aida Todri-Sanial:
Physical description and analysis of doped carbon nanotube interconnects. 250-255 - Maria J. Avedillo, Juan Núñez:
Impact of pipeline in the power performance of tunnel transistor circuits. 256-261 - Amir Najafi, Lennart Bamberg, Ardalan Najafi, Alberto García Ortiz:
Energy modeling of coupled interconnects including intrinsic misalignment effects. 262-267 - Hossein Aghababa, Mohammadreza Kolahdouz:
A novel leakage power reduction technique for nano-scaled CMOS digital integrated circuits. 268-274 - Konstantinos Railis, Vasileios Tsoutsouras, Sotirios Xydis, Dimitrios Soudris:
Energy profile analysis of Zynq-7000 programmable SoC for embedded medical processing: Study on ECG arrhythmia detection. 275-282 - Matthias Jung, Deepak M. Mathew, Éder F. Zulian, Christian Weis, Norbert Wehn:
A new bank sensitive DRAMPower model for efficient design space exploration. 283-288 - Klaus Hofmann, Tu Darmstadt:
The long way to power efficient, high performance DRAMs. 289-290 - Nasibeh Nasiri, Philip Colangelo, Oren Segal, Martin Margala, Wim Vanderbauwhede:
Document classification systems in heterogeneous computing environments. 291-295 - Luca Larcher, Francesco Maria Puglisi, Andrea Padovani, Luca Vandelli, Paolo Pavan:
Multiscale modeling of electron-ion interactions for engineering novel electronic devices and materials. 296-300 - Sebastian Volz, Haoxue Han:
Optimized few layer graphene for heat spreading. 301-303
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