Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDDesign Automation for Embedded Systems, Volume 19
Volume 19, Numbers 1-2, March 2015
- Calin Glitia, Julien DeAntoni
, Frédéric Mallet, Jean-Vivien Millo, Pierre Boulet, Abdoulaye Gamatié:
Progressive and explicit refinement of scheduling for multidimensional data-flow applications using UML MARTE. 1-33 - Hyeongbae Park, Jingzhe Xu, Jeong-Hoon Ji, Jusung Park, Gyun Woo:
Design methodology for on-chip-based processor debugger. 35-57 - Davide Bertozzi, Giorgos Dimitrakopoulos, José Flich, Sören Sonntag:
The fast evolving landscape of on-chip communication - Selected future challenges and research avenues. 59-76 - Bo-Kyeong Kim, Dong-Ho Lee:
LSB-Tree: a log-structured B-Tree index structure for NAND flash SSDs. 77-100 - Se Jin Kwon, Tae-Sun Chung:
Data pattern aware FTL for SLC+MLC hybrid SSD. 101-127 - Mirela Alistar, Paul Pop, Jan Madsen:
Redundancy optimization for error recovery in digital microfluidic biochips. 129-159 - Joon-Young Paik, Tae-Sun Chung, Eun-Sun Cho:
Application-aware deduplication for performance improvement of flash memory. 161-188 - Brahim Al Farisi, Karel Heyse, Karel Bruneel, João M. P. Cardoso, Dirk Stroobandt:
Enabling FPGA routing configuration sharing in dynamic partial reconfiguration. 189-221
Volume 19, Number 3, September 2015
- Mariem Turki, Zied Marrakchi, Habib Mehrez, Mohamed Abid:
Signal multiplexing approach to improve inter-FPGA bandwidth of prototyping platform. 223-242 - Luiza Gheorghe Iugan, Hanifa Boucheneb, Gabriela Nicolescu:
A generic conceptual framework based on formal representation for the design of continuous/discrete co-simulation tools. 243-275 - Emad Ebeid, Franco Fummi, Davide Quaglia:
HDL code generation from UML/MARTE sequence diagrams for verification and synthesis. 277-299 - François Duhem, Fabrice Muller, Robin Bonamy, Sébastien Bilavarn:
FoRTReSS: a flow for design space exploration of partially reconfigurable systems. 301-326
Volume 19, Number 4, December 2015
- Lisane B. de Brisolara, Ricardo Santos Ferreira:
SBESC 2013 guest editor's introduction. 327-328 - Fernanda M. Capella, Marcelo Brandalero, Luigi Carro, Antonio Carlos Schneider Beck:
A multiple-ISA reconfigurable architecture. 329-344 - Rosane Fátima Passarini, Jean-Marie Farines, João M. Fernandes, Leandro Buss Becker:
Cyber-physical systems design: transition from functional to architectural models. 345-366 - Ramon Hugo de Souza, Stefano Savazzi, Leandro Buss Becker:
Network design and planning of wireless embedded systems for industrial automation - Applications and case studies in oil refineries. 367-388 - Jiaxing Zhang, Gunar Schirner:
Towards closing the specification gap by integrating algorithm-level and system-level design. 389-419
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-15 20:34 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
