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2010 – 2019
- 2015
[j5]Brahim Al Farisi, Karel Heyse, Karel Bruneel, João M. P. Cardoso
, Dirk Stroobandt:
Enabling FPGA routing configuration sharing in dynamic partial reconfiguration. Des. Autom. Embed. Syst. 19(1-2): 189-221 (2015)- [j4]Dionisios N. Pnevmatikatos, Kyprianos Papadimitriou, Tobias Becker, Peter Böhm, Andreas Brokalakis, Karel Bruneel, Catalin Bogdan Ciobanu, Tom Davidson, Georgi Gaydadjiev, Karel Heyse, Wayne Luk, Xinyu Niu, Ioannis Papaefstathiou, Danilo Pau, Oliver Pell, Christian Pilato, Marco D. Santambrogio, Donatella Sciuto, Dirk Stroobandt, Tim Todman, Elias Vansteenkiste:
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration. Microprocess. Microsystems 39(4-5): 321-338 (2015) - [j3]Karel Heyse, Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt:
TCONMAP: Technology Mapping for Parameterised FPGA Configurations. ACM Trans. Design Autom. Electr. Syst. 20(4): 48:1-48:27 (2015) - [j2]Tom Davidson, Elias Vansteenkiste, Karel Heyse, Karel Bruneel, Dirk Stroobandt:
Identification of Dynamic Circuit Specialization Opportunities in RTL Code. ACM Trans. Reconfigurable Technol. Syst. 8(1): 4:1-4:24 (2015) - [j1]Karel Heyse, Jente Basteleus, Brahim Al Farisi, Dirk Stroobandt, Oliver Kadlcek, Oliver Pell:
On the Impact of Replacing Low-Speed Configuration Buses on FPGAs with the Chip's Internal Configuration Infrastructure. ACM Trans. Reconfigurable Technol. Syst. 9(1): 6:1-6:18 (2015) - [c10]Karel Heyse, Dirk Stroobandt:
Avoiding transitional effects in dynamic circuit specialisation on FPGAs. DAC 2015: 159:1-159:6 - [c9]Berg Severens, Elias Vansteenkiste, Karel Heyse, Dirk Stroobandt:
Estimating circuit delays in FPGAs after technology mapping. FPL 2015: 1-4 - 2014
- [c8]Karel Heyse, Dirk Stroobandt, Oliver Kadlcek, Oliver Pell:
On the Impact of Replacing a Low-Speed Memory Bus on the Maxeler Platform, Using the FPGA's Configuration Infrastructure. ARC 2014: 85-96 - [c7]Amit Kulkarni, Karel Heyse, Tom Davidson, Dirk Stroobandt:
Performance Evaluation of Dynamic Circuit Specialization on Xilinx FPGAs. FPGAworld 2014: 1:1-1:6 - [c6]Brahim Al Farisi, Karel Heyse, Dirk Stroobandt:
Reducing the overhead of dynamic partial reconfiguration for multi-mode circuits. FPT 2014: 282-283 - [c5]Amit Kulkarni, Tom Davidson, Karel Heyse, Dirk Stroobandt:
Improving reconfiguration speed for dynamic circuit specialization using placement constraints. ReConFig 2014: 1-6 - 2013
- [c4]Karel Heyse, Tom Davidson, Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt:
Efficient implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGAS. FPL 2013: 1-8 - 2012
- [c3]Karel Heyse, Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt:
Automating Reconfiguration Chain Generation for SRL-Based Run-Time Reconfiguration. ARC 2012: 1-12 - [c2]Karel Heyse, Karel Bruneel, Dirk Stroobandt:
Mapping logic to reconfigurable FPGA routing. FPL 2012: 315-321 - 2011
- [c1]Brahim Al Farisi, Karel Heyse, Karel Bruneel, Dirk Stroobandt:
Memory-Efficient and Fast Run-Time Reconfiguration of Regularly Structured Designs. FPL 2011: 171-176
Coauthor Index
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