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ORCIDIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 3
Volume 3, Number 1, January 1984
- Constantine N. Anagnostopoulos, Savvas G. Chamberlain:
Foreword. 1-2 - Edward M. Reingold, Kenneth J. Supowit:
A Hierarchy-Driven Amalgamation of Standard and Macro Cells. 3-11 - Gershon Kedem, Hiroyuki Watanabe:
Graph-Optimization Techniques for IC Layout and Compaction. 12-20 - David C. Smith, Richard Noto, Fred Borgini, Shanti S. Sharma, Joseph C. Werbickas:
The Variable Geometry Automated Universal Array Layout System (VGAUA). 20-26 - P. I. Jennings, Stanley L. Hurst, A. McDonald:
A Highly Routable ULM Gate Array and Its Automated Customizaton. 27-40 - Sani R. Nassif, Andrzej J. Strojwas, Stephen W. Director:
FABRICS II: A Statistically Based IC Fabrication Process Simulator. 40-46 - O. Melstrand, Eamonn O'Neill, Gerald E. Sobelman, D. Dokos:
A Data Base Driven Automated System for MOS Device Characterization, Parameter Optimization and Modeling. 47-51 - Siegfried Selberherr
, Christian A. Ringhofer:
Implications of Analytical Investigations About the Semiconductor Equations on Device Modeling Programs. 52-64 - A. M. Mazzone, G. Rocca:
Three-Dimensional Monte Carlo Simulations--Part I: Implanted Profiles for Dopants in Submicron Device. 64-71 - Yannis P. Tsividis, Guido Masetti:
Problems in Precision Modeling of the MOS Transistor for Analog Applications. 72-79 - Dileep A. Divekar, Richard I. Dowell:
A Depletion-Mode MOSFET Model for Circuit Simulation. 80-87 - John K. Ousterhout:
Corner Stitching: A Data-Structuring Technique for VLSI Layout Tools. 87-100 - Dileep A. Divekar:
DC Statistical Circuit Analysis for Bipolar IC's Using Parameter Correlations-An Experimental Example. 101-103 - Allan L. Silburt, Richard C. Foss, William F. Petrie:
An Efficient MOS Transistor Model for Computer-Aided Design. 104-111
Volume 3, Number 2, April 1984
- Claudio Turchetti, Guido Masetti:
A CAD-Oriented Analytical MOSFET Model for High-Accuracy Applications. 117-122 - Sharad C. Seth, Vishwani D. Agrawal:
Characterizing the LSI Yield Equation from Wafer Test Data. 123-126 - Thomas A. Johnson, Ronald W. Knepper, Victor Marcello, Wen Wang:
Chip Substrate Resistance Modeling Technique for Integrated Circuit Design. 126-134 - Erich Barke:
A Network Comparison Algorithm for Layout Verification of Integrated Circuits. 135-141 - Fabio Somenzi, Silvano Gai, Marco Mezzalama, Paolo Prinetto:
PART: Programmable Array Testing Based on a Partitioning Algorithm. 142-149 - David J. Lu, Edward J. McCluskey:
Quantitative Evaluation of Self-Checking Circuits. 150-155 - Yun Kang Chen, Mei Lun Liu:
Three-Layer Channel Routing. 156-163
Volume 3, Number 3, July 1984
- V. Visvanathan, Alberto L. Sangiovanni-Vincentelli:
A Computational Approach for the Diagnosability of Dynamical Circuits. 165-171 - Takeshi Tokuda, Jiro Korematsu, Osamu Tomisawa, Sotoju Asai, Isao Ohkura, Tatsuya Enomoto:
A Hierarchical Standard Cell Approach for Custom VLSI Design. 172-177 - Tom Tsan-Kuo Tarng, Malgorzata Marek-Sadowska, Ernest S. Kuh:
An Efficient Single-Row Routing Algorithm. 178-183 - Malgorzata Marek-Sadowska:
An Unconstrained Topological Via Minimization Problem for Two-Layer Routing. 184-190 - Jack R. Egan, C. L. Liu:
Bipartite Folding and Partitioning of a PLA. 191-199 - John P. Hayes:
Fault Modeling for Digital MOS Integrated Circuits. 200-208 - Fredrick J. Hill, Zainalabedin Navabi, Chen H. Chiang, Duan-Ping Chen, Manzer Masud:
Hardware Compilation from an RTL to a Storage Logic Array Target. 208-217 - Chung-Kuan Cheng, Ernest S. Kuh:
Module Placement Based on Resistive Network Optimization. 218-225 - Ronald A. Rohrer, Hassan Nosrati, Kenneth W. Heizer:
Quasi-Static Control of Explicit Algorithms for Transient Analysis. 226-234 - Sangyong Han, Sartaj Sahni:
Single-Row Routing in Narrow Streets. 235-241 - John K. Ousterhout:
The User Interface and Implementation of an IC Layout Editor. 242-249 - H. Nelson Brady:
An Approach to Topological Pin Assignment. 250-255 - Giovanni De Micheli, Alberto L. Sangiovanni-Vincentelli:
Correction to "Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications". 256
Volume 3, Number 4, October 1984
- Teofilo F. Gonzalez:
An Approximation Problem for the Multi-Via Assignment Problem. 257-264 - Rob A. Rutenbar, Trevor N. Mudge, Daniel E. Atkins:
A Class of Cellular Architectures to Support Physical Design Automation. 264-278 - Dale E. Hocevar, Michael R. Lightner, Timothy N. Trick:
An Extrapolated Yield Approximation Technique for Use in Yield Maximization. 279-287 - James R. Armstrong:
Chip Level Modeling of LSI Devices. 288-297 - Jeong-Tyng Li, Malgorzata Marek-Sadowska:
Global Routing for Gate Array. 298-307 - A. Richard Newton, Alberto L. Sangiovanni-Vincentelli:
Relaxation-Based Electrical Simulation. 308-331 - Tzu-Mu Lin, Carver Mead:
Signal Delay in General RC Networks. 331-349
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