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Suhaib A. Fahmy

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Abhishek Kumar Jain

> Home > Persons > Suhaib A. Fahmy

Publications

2022
[j35]
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  - journals/tpds/JainMF22
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Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy:
Coarse Grained FPGA Overlay for Rapid Just-In-Time Accelerator Compilation. IEEE Trans. Parallel Distributed Syst. 33(6): 1478-1490 (2022)
2020
[c73]
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  - conf/iscas/LiVMFJ20
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Xiangwei Li, Kizheppatt Vipin, Douglas L. Maskell, Suhaib A. Fahmy, Abhishek Kumar Jain:
High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay. ISCAS 2020: 1-5
2018
[c67]
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  - conf/date/LiJMF18
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Xiangwei Li, Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy:
A time-multiplexed FPGA overlay with linear interconnect. DATE 2018: 1075-1080
2017
[i3]
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  - journals/corr/JainMF17
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Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy:
Resource-Aware Just-in-Time OpenCL Compiler for Coarse-Grained FPGA Overlays. CoRR abs/1705.02730 (2017)
2016
[c62]
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  - conf/dasc/JainMF16
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Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy:
Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs? DASC/PiCom/DataCom/CyberSciTech 2016: 586-593
[c60]
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Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy:
Throughput oriented FPGA overlays using DSP blocks. DATE 2016: 1628-1633
[c59]
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  - conf/fccm/JainLSMF16
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Abhishek Kumar Jain, Xiangwei Li, Pranjul Singhai, Douglas L. Maskell, Suhaib A. Fahmy:
DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect. FCCM 2016: 1-8
[i1]
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Xiangwei Li, Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy:
An Area-Efficient FPGA Overlay using DSP Block based Time-multiplexed Functional Units. CoRR abs/1606.06460 (2016)
2015
[j13]
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  - journals/sigarch/JainLFM15
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Abhishek Kumar Jain, Xiangwei Li, Suhaib A. Fahmy, Douglas L. Maskell:
Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq. SIGARCH Comput. Archit. News 43(4): 28-33 (2015)
[c47]
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Abhishek Kumar Jain, Suhaib A. Fahmy, Douglas L. Maskell:
Efficient Overlay Architecture Based on DSP Blocks. FCCM 2015: 25-28
2014
[j8]
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  - journals/vlsisp/JainPCFM14
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Abhishek Kumar Jain, Khoa Dang Pham, Jin Cui, Suhaib A. Fahmy, Douglas L. Maskell:
Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform. J. Signal Process. Syst. 77(1-2): 61-76 (2014)
2013
[c30]
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  - conf/asap/PhamJCFM13
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Khoa Dang Pham, Abhishek Kumar Jain, Jin Cui, Suhaib A. Fahmy, Douglas L. Maskell:
Microkernel hypervisor for a hybrid ARM-FPGA platform. ASAP 2013: 219-226

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