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ORCIDDATE 2016: Dresden, Germany
- Luca Fanucci, Jürgen Teich:
2016 Design, Automation & Test in Europe Conference & Exhibition, DATE 2016, Dresden, Germany, March 14-18, 2016. IEEE 2016, ISBN 978-3-9815-3707-9 - Jörg Henkel, Santiago Pagani, Heba Khdr, Florian Kriebel, Semeen Rehman, Muhammad Shafique:
Towards performance and reliability-efficient computing in the dark silicon era. 1-6 - Ali Pahlevan, Javier Picorel, Arash Pourhabibi Zarandi, Davide Rossi, Marina Zapater, Andrea Bartolini, Pablo García Del Valle, David Atienza, Luca Benini, Babak Falsafi:
Towards near-threshold server processors. 7-12 - Robert Perricone, Xiaobo Sharon Hu, Joseph Nahas, Michael T. Niemier:
Can beyond-CMOS devices illuminate dark silicon? 13-18 - Korosh Vatanparvar, Mohammad Abdullah Al Faruque:
OTEM: Optimized Thermal and Energy Management for Hybrid Electrical Energy Storage in Electric Vehicles. 19-24 - Sebastian Kehr, Milos Panic, Eduardo Quiñones, Bert Böddeker, Jorge Becerril Sandoval, Jaume Abella, Francisco J. Cazorla, Günter Schäfer:
Supertask: Maximizing runnable-level parallelism in AUTOSAR applications. 25-30 - Daniel Thiele, Rolf Ernst:
Formal analysis based evaluation of software defined networking for time-sensitive Ethernet. 31-36 - Shanker Shreejith, Bezborah Anshuman, Suhaib A. Fahmy:
Accelerated Artificial Neural Networks on FPGA for fault detection in automotive systems. 37-42 - Jian Kuang, Evangeline F. Y. Young:
Optimization for Multiple Patterning Lithography with cutting process and beyond. 43-48 - Ahmed Awad, Atsushi Takahashi, Chikaaki Kodama:
A fast manufacturability aware Optical Proximity Correction (OPC) algorithm with adaptive wafer image estimation. 49-54 - Woohyun Chung, Seongbo Shim, Youngsoo Shin:
Redundant via insertion in directed self-assembly lithography. 55-60 - Kwangsoo Han, Andrew B. Kahng, Jiajia Li:
Improved performance of 3DIC implementations through inherent awareness of mix-and-match die stacking. 61-66 - Yingnan Cui, Wei Zhang, Bingsheng He:
A discrete thermal controller for chip-multiprocessors. 67-72 - Simon J. Hollis, Steve Kerrison:
Swallow: Building an energy-transparent many-core embedded real-time system. 73-78 - Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang:
A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements. 79-84 - Xiuhong Li, Yun Liang:
Efficient kernel management on GPUs. 85-90 - Damien Hardy, Isabelle Puaut, Yiannakis Sazeides:
Probabilistic WCET estimation in presence of hardware for mitigating the impact of permanent faults. 91-96 - Zaid Al-bayati, Jonah Caplan, Brett H. Meyer, Haibo Zeng:
A four-mode model for efficient fault-tolerant mixed-criticality systems. 97-102 - Eberle A. Rambo, Selma Saidi, Rolf Ernst:
Providing formal latency guarantees for ARQ-based protocols in Networks-on-Chip. 103-108 - Zeye Liu, Ben Niewenhuis, Soumya Mittal, R. D. (Shawn) Blanton:
Achieving 100% cell-aware coverage by design. 109-114 - Mahdi Nikdast, Gabriela Nicolescu, Jelena Trajkovic, Odile Liboiron-Ladouceur:
Modeling fabrication non-uniformity in chip-scale silicon photonic interconnects. 115-120 - Changhai Liao, Jun Tao, Xuan Zeng, Yangfeng Su, Dian Zhou, Xin Li:
Efficient spatial variation modeling via robust dictionary learning. 121-126 - Bohan Yang, Vladimir Rozic, Nele Mentens, Wim Dehaene, Ingrid Verbauwhede:
TOTAL: TRNG on-the-fly testing for attack detection using Lightweight hardware. 127-132 - Maxime Lecomte, Jacques J. A. Fournier, Philippe Maurine:
On-chip fingerprinting of IC topology for integrity verification. 133-138 - Muhammad Yasin, Samah Mohamed Saeed, Jeyavijayan Rajendran, Ozgur Sinanoglu:
Activation of logic encrypted chips: Pre-test or post-test? 139-144 - Syed Shakib Sarwar, Swagath Venkataramani, Anand Raghunathan, Kaushik Roy:
Multiplier-less Artificial Neurons exploiting error resiliency for energy-efficient neural computing. 145-150 - Gopalakrishnan Srinivasan, Parami Wijesinghe, Syed Shakib Sarwar, Akhilesh Jaiswal, Kaushik Roy:
Significance driven hybrid 8T-6T SRAM for energy-efficient synaptic storage in artificial neural networks. 151-156 - Minho Ju, Hyeonggyu Kim, Soontae Kim:
Network delay-aware energy management for mobile systems. 157-162 - Sunghyun Park, Alice Wang, Uming Ko, Li-Shiuan Peh, Anantha P. Chandrakasan:
Enabling simultaneously bi-directional TSV signaling for energy and area efficient 3D-ICs. 163-168 - Jens Trommer, Andre Heinzig, Tim Baldauf, Thomas Mikolajick, Walter M. Weber, Michael Raitza, Marcus Völp
:
Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits. 169-174 - Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Robert Wille, Giovanni De Micheli:
Exploiting inherent characteristics of reversible circuits for faster combinational equivalence checking. 175-180 - Junchul Choi, Donghyun Kang, Soonhoi Ha:
Conservative modeling of shared resource contention for dependent tasks in partitioned multi-core systems. 181-186 - Daniel Thiele, Rolf Ernst:
Formal worst-case timing analysis of Ethernet TSN's burst-limiting shaper. 187-192 - Alessandro Biondi, Giorgio C. Buttazzo:
Real-time analysis of engine control applications with speed estimation. 193-198 - Lin Li, Albrecht Mayer:
Trace-based analysis methodology of program flash contention in embedded multicore systems. 199-204 - Anteneh Gebregiorgis, Saman Kiamehr, Fabian Oboril, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
A cross-layer analysis of Soft Error, aging and process variation in Near Threshold Computing. 205-210 - Hsuan-Ming Huang, Yuwen Lin, Charles H.-P. Wen:
Fast-yet-accurate variation-aware current and voltage modelling of radiation-induced transient fault. 211-216 - Marc Riera, Ramon Canal, Jaume Abella, Antonio González:
A detailed methodology to compute Soft Error Rates in advanced technologies. 217-222 - Ahmet Unutulmaz, Domenik Helms, Reef Eilers, Malte Metzdorf, Ben Kaczer, Wolfgang Nebel:
Analysis of NBTI effects on high frequency digital circuits. 223-228 - Kai Huang, Biao Hu, Jan Botsch, Nikhil Madduri, Alois C. Knoll:
A scalable lane detection algorithm on COTSs with OpenCL. 229-232 - Dennis Hospach, Stefan Müller, Wolfgang Rosenstiel, Oliver Bringmann:
Simulation of falling rain for robustness testing of video-based surround sensing systems. 233-236 - Yusuke Sakumoto, Ittetsu Taniguchi:
Proposal for fast directional energy interchange used in MCMC-based autonomous decentralized mechanism toward resilient microgrid. 237-240 - Takeshi Ihara, Toshiyuki Hongo, Atsushi Takahashi, Chikaaki Kodama:
Grid-based Self-Aligned Quadruple Patterning aware two dimensional routing pattern. 241-244 - Hsueh-Ju Lu, En-Jang Jang, Ang Lu, Yu Ting Zhang, Yu-He Chang, Chi-Hung Lin, Rung-Bin Lin:
Practical ILP-based routing of standard cells. 245-248 - Daohang Shi, Azadeh Davoodi, Jeffrey T. Linderoth:
A procedure for improving the distribution of congestion in global routing. 249-252 - Rahul Jain, Preeti Ranjan Panda, Sreenivas Subramoney:
Machine Learned Machines: Adaptive co-optimization of caches, cores, and On-chip Network. 253-256 - Syed Md Jakaria Abdullah, Kai Lampka, Wang Yi:
Improving performance by monitoring while maintaining worst-case guarantees. 257-260 - Rajendra Bishnoi, Fabian Oboril, Mehdi Baradaran Tahoori:
Fault Tolerant Non-Volatile spintronic flip-flop. 261-264 - Yasser Moursy, Hao Zou, Ramy Iskander, Pierre Tisserand, Dieu-My Ton, Giuseppe Pasetti, Ehrenfried Seebacher, Alexander Steinmair, Thomas Gneiting, Heidrun Alius:
Towards automatic diagnosis of minority carriers propagation problems in HV/HT automotive smart power ICs. 265-268 - Zongbin Liu, Qinglong Zhang, Cunqing Ma, Changting Li, Jiwu Jing:
HPAZ: A high-throughput pipeline architecture of ZUC in hardware. 269-272 - Elena Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto:
Towards a highly reliable SRAM-based PUFs. 273-276 - Fengchao Zhang, Shuo Yang, Jim Plusquellic, Swarup Bhunia:
Current based PUF exploiting random variations in SRAM cells. 277-280 - Taesik Na, Saibal Mukhopadhyay:
Behavioral modeling of timing slack variation in digital circuits due to power supply noise. 281-284 - Pei-Chun Lin, Yu-Hsuan Pai, Yu-Hsiang Chiu, Shao-Yuan Fang, Charlie Chung-Ping Chen:
Lossless compression algorithm based on dictionary coding for multiple e-beam direct write system. 285-288 - Edoardo Fusella, Alessandro Cilardo:
PhoNoCMap: An application mapping tool for photonic networks-on-chip. 289-292 - Risat Mahmud Pathan:
Design of an efficient ready queue for earliest-deadline-first (EDF) scheduler. 293-296 - Nils Koppaetzky, Malte Metzdorf, Reef Eilers, Domenik Helms, Wolfgang Nebel:
RT level timing modeling for aging prediction. 297-300 - Bratislav Tasic, Jos J. Dohmen, Rick Janssen, E. Jan W. ter Maten, Theo G. J. Beelen, Roland Pulch:
Fast time-domain simulation for reliable fault detection. 301-306 - Wim Schoenmaker, Peter Meuris, Christian Strohm, Caren Tischendorf:
Holistic coupled field and circuit simulation. 307-312 - Nicodemus Banagaaya, Lihong Feng, Wim Schoenmaker, Peter Meuris, Aarnout Wieers, Renaud Gillon, Peter Benner:
Model Order Reduction for nanoelectronics coupled problems with many inputs. 313-318 - Piotr Putek, Peter Meuris, Roland Pulch, E. Jan W. ter Maten, Michael Gunther, Wim Schoenmaker, Frederik Deleu, Aarnout Wieers:
Shape optimization of a power MOS device under uncertainties. 319-324 - Oscar M. Guillen, Dawin Schmidt, Georg Sigl:
Practical evaluation of code injection in encrypted firmware updates. 325-330 - Yongje Lee, Jinyong Lee, Ingoo Heo, Dongil Hwang, Yunheung Paek:
Integration of ROP/JOP monitoring IPs in an ARM-based SoC. 331-336 - Pramod Subramanyan, Sharad Malik, Hareesh Khattri, Abhranil Maiti, Jason M. Fung:
Verifying information flow properties of firmware using symbolic execution. 337-342 - Daniele Jahier Pagliari, Massimo Poncino, Enrico Macii:
Low-overhead adaptive constrast enhancement and power reduction for OLEDs. 343-348 - Andres Gomez, Lukas Sigrist, Michele Magno, Luca Benini, Lothar Thiele:
Dynamic energy burst scaling for transiently powered systems. 349-354 - Dinko Oletic, Vedran Bilas, Michele Magno, Norbert Felber, Luca Benini:
Low-power multichannel spectro-temporal feature extraction circuit for audio pattern wake-up. 355-360 - Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, Costin Anghel:
3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications. 361-366 - Xunzhao Yin, Behnam Sedighi, Michael T. Niemier, Xiaobo Sharon Hu:
Design of latches and flip-flops using emerging tunneling devices. 367-372 - Mohsen Imani, Shruti Patil, Tajana Simunic Rosing:
MASC: Ultra-low energy multiple-access single-charge TCAM for approximate computing. 373-378 - Anuj Pathania, Vanchinathan Venkataramani, Muhammad Shafique, Tulika Mitra, Jörg Henkel:
Distributed fair scheduling for many-cores. 379-384 - Kai Lampka, Björn Forsberg:
Keep it slow and in time: Online DVFS with hard real-time workloads. 385-390 - Yejia Di, Liang Shi, Kaijie Wu, Chun Jason Xue:
Exploiting process variation for retention induced refresh minimization on flash memory. 391-396 - Fábio Passos, Reinier Gonzalez-Echevarria, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández:
Accurate synthesis of integrated RF passive components using surrogate models. 397-402 - Anindya Mukherjee, Andreas Pawlak, Michael Schröter, Didier Céli, Zoltan Huszka:
Implementation and quality testing for compact models implemented in Verilog-A. 403-408 - Ya Wang, Di Gao, Dani A. Tannir, Peng Li:
Multi-harmonic nonlinear modeling of low-power PWM DC-DC converters operating in CCM and DCM. 409-414 - Stephan Herrmann, Wolfgang Utschick:
Availability and interpretability of optimal control for criticality estimation in vehicle active safety. 415-420 - Alon Ascoli, Ronald Tetzlaff, Leon O. Chua, John Paul Strachan, R. Stanley Williams:
Fading memory effects in a memristor for Cellular Nanoscale Network applications. 421-425 - Massimiliano Di Ventra, Fabio L. Traversa:
Digital Memcomputing Machines. 426 - Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Anne Siemon, Eike Linn, Rainer Waser, Anupam Chattopadhyay, Giovanni De Micheli:
The Programmable Logic-in-Memory (PLiM) computer. 427-432 - Duo Liu, Cunxi Yu, Xiangyu Zhang, Daniel E. Holcomb:
Oracle-guided incremental SAT solving to reverse engineer camouflaged logic circuits. 433-438 - David El-Baze, Jean-Baptiste Rigaud, Philippe Maurine:
A fully-digital EM pulse detector. 439-444 - Charalampos Ananiadis, Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle:
On the development of a new countermeasure based on a laser attack RTL fault model. 445-450 - Qixiang Zhang, Liangzhen Lai, Mark Gottscho, Puneet Gupta:
Multi-story power distribution networks for GPUs. 451-456 - Alireza Shafaei, Massoud Pedram:
Energy-efficient cache memories using a dual-Vt 4T SRAM cell with read-assist techniques. 457-462 - Taeyoung Kim, Xin Huang, Hai-Bao Chen, Valeriy Sukharev, Sheldon X.-D. Tan:
Learning-based dynamic reliability management for dark silicon processor considering EM effects. 463-468 - Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Xiling Yin, Wenqin Huangfu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie, Huazhong Yang:
MNSIM: Simulation platform for memristor-based neuromorphic computing system. 469-474 - Priyadarshini Panda, Abhronil Sengupta, Kaushik Roy:
Conditional Deep Learning for energy-efficient and enhanced pattern recognition. 475-480 - Sai Zhang, Naresh R. Shanbhag:
Probabilistic Error Models for machine learning kernels implemented on stochastic nanoscale fabrics. 481-486 - Nicolas Ventroux, Tanguy Sassolas:
A new parallel SystemC kernel leveraging manycore architectures. 487-492 - Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid, Dietmar Petras, Andreas Hoffmann:
SystemC-link: Parallel SystemC simulation using time-decoupled segments. 493-498 - Leandro Gil, Martin Radetzki:
Orthogonal signal modeling and operational computation of AMS circuits for fast and accurate system simulation. 499-504 - Athanasios Dimakos, Haralampos-G. D. Stratigopoulos, Alexandre Siligaris, Salvador Mir, Emeric de Foucauld:
Built-in test of millimeter-Wave circuits based on non-intrusive sensors. 505-510 - Jongho Kim, Gunhee Lee, Kiyoung Choi, Yonghwan Kim, Wook Kim, Kyung Tae Do, Jung Yun Choi:
Adaptive delay monitoring for wide voltage-range operation. 511-516 - Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura, Kunihiro Asada:
Analytical design optimization of sub-ranging ADC based on stochastic comparator. 517-522 - Alexander Stühring, Günter Ehmen, Sibylle B. Fröschle:
Analyzing the impact of injected sensor data on an Advanced Driver Assistance System using the OP2TIMUS prototyping platform. 523-526 - Nicole Fern, Ismail San, Çetin Kaya Koç, Kwang-Ting Cheng:
Hardware Trojans in incompletely specified on-chip bus systems. 527-530 - Emanuele Del Sozzo, Gianluca C. Durelli, E. M. G. Trainiti, Antonio Miele, Marco D. Santambrogio, Cristiana Bolchini:
Workload-aware power optimization strategy for asymmetric multiprocessors. 531-534 - Anup Das, Geoff V. Merrett, Bashir M. Al-Hashimi:
The slowdown or race-to-idle question: Workload-aware energy optimization of SMT multicore platforms under process variation. 535-538 - Matina Maria Trompouki, Leonidas Kosmidis:
Towards general purpose computations on low-end mobile GPUs. 539-542 - S. V. Sandeep Avvaru, Chen Zhou, Saroj Satapathy, Yingjie Lao, Chris H. Kim, Keshab K. Parhi:
Estimating delay differences of arbiter PUFs using silicon data. 543-546 - Marc Lacruche, Noemie Beringuier-Boher, Jean-Max Dutertre, Jean-Baptiste Rigaud, Edith Kussener:
On the use of Forward Body Biasing to decrease the repeatability of laser-induced faults. 547-550 - Srihari Yechangunja, Raj Shekhar, Mohit Kumar, Nikhil Tripathi, Abhishek Mittal, Abhishek Ranjan, Jianfeng Liu, Minyoung Mo, Kyung Tae Do, Jung Yun Choi, SungHo Park:
Sequential analysis driven reset optimization to improve power, area and routability. 551-554 - Bo Liu, Anna Nikolaeva:
Efficient global optimization of MEMS based on surrogate model assisted evolutionary algorithm. 555-558 - Yuliia Romenska, Florence Maraninchi:
Efficient monitoring of loose-ordering properties for SystemC/TLM. 559-562 - K. Naveen, Dinesh Kumar Sharma:
Testable design of repeaterless low swing on-chip interconnect. 563-566 - Ta-Tung Yen, Bin Yu, Visvesh S. Sathe:
All-digital hybrid-control buck converter for Integrated Voltage Regulator applications. 567-570 - Marco Casale-Rossi, Giovanni De Micheli, Antun Domic, Enrico Macii, Domenico Rossi, Joseph Sawicki:
Panel: Looking backwards and forwards. 571-575 - Victor M. van Santen, Hussam Amrouch, Narendra Parihar, Souvik Mahapatra, Jörg Henkel:
Aging-aware voltage scaling. 576-581 - Tuo Li, Jude Angelo Ambrose, Sri Parameswaran:
RECORD: Reducing register traffic for checkpointing in embedded processors. 582-587 - Philipp Schläfer, Chu-Hsiang Huang, Clayton Schoeny, Christian Weis, Yao Li, Norbert Wehn, Lara Dolecek:
Error resilience and energy efficiency: An LDPC decoder design study. 588-593 - Apostolos Kokolis, Alexandros Mavrogiannis, Dimitrios Rodopoulos, Christos Strydis, Dimitrios Soudris:
Runtime interval optimization and dependable performance for application-level checkpointing. 594-599 - Benjamin A. Bjørnseth, Asbjørn Djupdal, Lasse Natvig:
A systematic approach to automated construction of power emulation models. 600-605 - Alessandro Danese, Graziano Pravadelli, Ivan Zandona:
Automatic generation of power state machines through dynamic mining of temporal assertions. 606-611 - Shubham Jain, Swagath Venkataramani, Anand Raghunathan:
Approximation through logic isolation for the design of quality configurable circuits. 612-617 - Morten Chabert Eskesen, Paul Pop, Seetal Potluri:
Architecture synthesis for cost-constrained fault-tolerant flow-based biochips. 618-623 - Mengchu Li, Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Sieve-valve-aware synthesis of flow-based microfluidic biochips considering specific biological execution limitations. 624-629 - Mohamed Ibrahim, Krishnendu Chakrabarty, Kristin Scott:
Integrated and real-time quantitative analysis using cyberphysical digital-microfluidic biochips. 630-635 - Amir Aminifar, Paulo Tabuada, Petru Eles, Zebo Peng:
Self-triggered controllers and hard real-time guarantees. 636-641 - Yuankun Xue, Saul Rodriguez, Paul Bogdan:
A spatio-temporal fractal model for a CPS approach to brain-machine-body interfaces. 642-647 - Nathan Allen, Sidharta Andalam, Partha S. Roop, Avinash Malik, Mark Trew, Nitish D. Patel:
Modular code generation for emulating the electrical conduction system of the human heart. 648-653 - Juan Valencia, E. P. van Horssen, Dip Goswami, W. P. M. H. Heemels, Kees Goossens:
Resource utilization and Quality-of-Control trade-off for a composable platform. 654-659 - Haider A. F. Almurib, T. Nandha Kumar, Fabrizio Lombardi:
Inexact designs for approximate low power addition by cell replacement. 660-665 - Soumya Banerjee, Wenjing Rao:
A general approach for highly defect tolerant Parallel Prefix Adder design. 666-671 - Martin Omaña, A. Fiore, Cecilia Metra:
Inverters' self-checking monitors for reliable photovoltaic systems. 672-677 - Manolis Marazakis, John Goodacre, Didier Fuin, Paul M. Carpenter, John Thomson, Emil Matús, Antimo Bruno, Per Stenström, Jérôme Martin, Yves Durand, Isabelle Dor:
EUROSERVER: Share-anything scale-out micro-server design. 678-683 - Oscar Palomar, Santhosh Kumar Rethinagiri, Gulay Yalcin, J. Rubén Titos Gil, Pablo Prieto, Emma Torrella, Osman S. Unsal, Adrián Cristal, Pascal Felber, Anita Sobe, Yaroslav Hayduk, Mascha Kurpicz, Christof Fetzer, Thomas Knauth, Malte Schneegaß, Jens Struckmeier, Dragomir Milojevic:
Energy minimization at all layers of the data center: The ParaDIME project. 684-689 - Kostas Katrinis, Dimitris Syrivelis, Dionisios N. Pnevmatikatos, Georgios Zervas, Dimitris Theodoropoulos, Iordanis Koutsopoulos, K. Hasharoni, Daniel Raho, Christian Pinto, Felix Espina, Sergio López-Buedo, Qianqiao Chen, Mario Nemirovsky, Damian Roca, H. Klos, T. Berends:
Rack-scale disaggregated cloud data centers: The dReDBox project vision. 690-695 - Iakovos Mavroidis, Ioannis Papaefstathiou, Luciano Lavagno, Dimitrios S. Nikolopoulos, Dirk Koch, John Goodacre, Ioannis Sourdis, Vassilis Papaefstathiou, Marcello Coppola, Manuel Palomino:
ECOSCALE: Reconfigurable computing and runtime system for future exascale systems. 696-701 - José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Alessandro Cilardo, William Fornaciari, Ynse Hoornenborg, Mario Kovac, Bruno Maitre, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Fabrice Roudet, Rafael Tornero, Davide Zoni:
Enabling HPC for QoS-sensitive applications: The MANGO approach. 702-707