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ORCIDJia Yu 0008
Person information
- affiliation: University of California Riverside, CA, USA
Other persons with the same name
- Jia Yu — disambiguation page
- Jia Yu 0001
![[0000-0003-1340-6475]](https://dblp.org/img/orcid-mark.12x12.png "0000-0003-1340-6475")
— Arizona State University, Tempe, AZ, USA - Jia Yu 0002 — Northwestern Polytechnical University, Xi'an, China
- Jia Yu 0003 — Qingdao University, College of Computer Science and Technology, Qingdao, China (and 2 more)
- Jia Yu 0004 — Nanyang Technological University, Singapore
- Jia Yu 0006 — Harbin Institute of Technology, Shenzhen, China
- Jia Yu 0007 — Shanghai Normal University, China (and 1 more)
- Jia Yu 0009 — University of Melbourne, VIC, Australia
- Jia Yu 0010 — Huazhong University of Science and Technology, Wuhan, China
- Jia Yu 0011 — Minzu University of China, Beijing, China
- Jia Yu 0012 — Hohai University, Nanjing, China
- Jia Yu 0013 — University of New South Wales, Sydney, Australia
- Jia Yu 0014 — Administrative College of JiangSu Province, Nanjing, China
- Jia Yu 0015 — University of California, Department of Mathematics, Berkeley, CA, USA
- Jia Yu 0016 — Ocean University of China, Qingdao, China
- Jia Yu 0017 — Seeburger China Inc., Shanghai, China
- Jia Yu 0018 — China Electronics Technology Cyber Security Co., Ltd.
- Jia Yu 0019 — University of Jinan, Jinan, China
- Jia Yu 0020 — Washington State University, USA (and 1 more)
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Journal Articles
- 2007
[j2]Yan Luo, Jia Yu, Jun Yang, Laxmi N. Bhuyan:
Conserving network processor power consumption by exploiting traffic variability. ACM Trans. Archit. Code Optim. 4(1): 4 (2007)- 2005
- [j1]Jun Yang, Jia Yu, Youtao Zhang:
A low energy cache design for multimedia applications exploiting set access locality. J. Syst. Archit. 51(10-11): 653-664 (2005)
Conference and Workshop Papers
- 2012
- [c8]Bin Liu, Bo Yuan, Huichen Dai, Hongbo Zhao, Jia Yu, Laxmi N. Bhuyan:
Improving the throughput and delay performance of network processors by applying push model. IWQoS 2012: 1-4 - 2010
- [c7]Bo Yuan, Hongbo Zhao, Chengchen Hu, Bin Liu, Jia Yu, Laxmi N. Bhuyan:
Experience on Applying Push Model to Packet Processors in High Performance Routers. GLOBECOM 2010: 1-5 - 2008
- [c6]Zhen Liu, Jia Yu, Xiaojun Wang, Bin Liu, Laxmi N. Bhuyan:
Revisiting the Cache Effect on Multicore Multithreaded Network Processors. DSD 2008: 317-324 - 2007
- [c5]Jia Yu, Jingnan Yao, Laxmi N. Bhuyan, Jun Yang:
Program Mapping onto Network Processors by Recursive Bipartitioning and Refining. DAC 2007: 805-810 - 2005
- [c4]Yan Luo, Jia Yu, Jun Yang, Laxmi N. Bhuyan:
Low power network processor design using clock gating. DAC 2005: 712-715 - [c3]Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin:
Assertion-Based Design Exploration of DVS in Network Processor Architectures. DATE 2005: 92-97 - [c2]Jia Yu, Jun Yang, Shaojie Chen, Yan Luo, Laxmi N. Bhuyan:
Enhancing Network Processor Simulation Speed with Statistical Input Sampling. HiPEAC 2005: 68-83 - 2004
- [c1]Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin:
Assertion-based power/performance analysis of network processor architectures. HLDVT 2004: 155-160
Informal and Other Publications
- 2007
- [i1]Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin:
Assertion-Based Design Exploration of DVS in Network Processor Architectures. CoRR abs/0710.4714 (2007)
Coauthor Index
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