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Remy Chevallier
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2010 – 2019
- 2010
- [c3]Abdelrezzak Bara, Pirouz Bazargan-Sabet, Remy Chevallier, Dominique Le Dû, Emmanuelle Encrenaz, Patricia Renault:
Formal Verification of Timed VHDL Programs. FDL 2010: 80-85
2000 – 2009
- 2009
- [j1]Remy Chevallier, Emmanuelle Encrenaz-Tiphène, Laurent Fribourg, Weiwen Xu:
Timed verification of the generic architecture of a memory circuit using parametric timed automata. Formal Methods Syst. Des. 34(1): 59-81 (2009) - 2006
- [c2]Remy Chevallier, Emmanuelle Encrenaz-Tiphène, Laurent Fribourg, Weiwen Xu:
Verification of the Generic Architecture of a Memory Circuit Using Parametric Timed Automata. FORMATS 2006: 113-127 - 2005
- [c1]Ghiath Al Sammane, Dominique Borrione, Remy Chevallier:
Verification of behavioral descriptions by combining symbolic simulation and automatic reasoning. ACM Great Lakes Symposium on VLSI 2005: 260-263
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last updated on 2024-04-25 05:51 CEST by the dblp team
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