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"Timed verification of the generic architecture of a memory circuit using ..."

Remy Chevallier et al. (2009)

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DOI: 10.1007/S10703-008-0061-X

access: closed

type: Journal Article

metadata version: 2020-03-13

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  - https://dblp.org/rec/journals/fmsd/ChevallierEFX09
Remy Chevallier, Emmanuelle Encrenaz-Tiphène, Laurent Fribourg, Weiwen Xu:
Timed verification of the generic architecture of a memory circuit using parametric timed automata. Formal Methods Syst. Des. 34(1): 59-81 (2009)

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