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Ichiro Kuroda
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2000 – 2009
- 2008
- [j19]Ichiro Kuroda:
Special Section on Signal Processing for Audio and Visual Systems and Its Implementations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(3): 721-722 (2008) - 2007
- [j18]Ichiro Kuroda, Shorin Kyo:
Media Processing LSI Architectures for Automotives - Challenges and Future Trends - . IEICE Trans. Electron. 90-C(10): 1850-1857 (2007) - 2006
- [j17]Ichiro Kuroda:
Special Section on Papers Selected from the 20th Symposium on Signal Processing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(8): 2099 (2006) - 2005
- [j16]Takahiro Kumura, Norio Kayama, Shinichi Shionoya, Kazuo Kumagiri, Takao Kusano, Makoto Yoshida, Masao Ikekawa, Ichiro Kuroda, Takao Nishitani:
Performance Evaluation of the AV CODEC on a Low-Power SPXK5SC DSP Core. IEICE Trans. Inf. Syst. 88-D(6): 1224-1230 (2005) - [j15]Atsushi Hatabu, Takashi Miyazaki, Ichiro Kuroda:
QVGA/CIF Resolution MPEG-4 Video Codec Based on a Low-Power and General-Purpose DSP. J. VLSI Signal Process. 39(1-2): 7-14 (2005) - [c18]Toru Yamada, Masao Ikekawa, Ichiro Kuroda:
Fast and accurate motion estimation algorithm by adaptive search range and shape selection. ICASSP (2) 2005: 897-900 - 2004
- [j14]Shorin Kyo, Takuya Koga, Shin'ichiro Okazaki, Ichiro Kuroda:
A 51.2 GOPS Programmable Video Recognition Processor for Vision-Based Intelligent Cruise Control Applications. IEICE Trans. Inf. Syst. 87-D(1): 136-145 (2004) - [c17]Yuichi Nakamura, Kohei Hosokawa, Ichiro Kuroda, Ko Yoshikawa, Takeshi Yoshimura:
A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication. DAC 2004: 299-304 - 2003
- [j13]Shorin Kyo, Takuya Koga, Shin'ichiro Okazaki, Ichiro Kuroda:
A 51.2-GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 four-way VLIW processing elements. IEEE J. Solid State Circuits 38(11): 1992-2000 (2003) - [c16]Atsushi Hatabu, Takashi Miyazaki, Ichiro Kuroda:
Optimization of decision-timing for early termination of SSDA-based block matching. ICASSP (2) 2003: 533-536 - [c15]Atsushi Hatabu, Takashi Miyazaki, Ichiro Kuroda:
Optimization of decision-timing for early termination of SSDA-based block matching. ICME 2003: 821-824 - 2002
- [j12]Ichiro Kuroda:
Asynchronous Multirate Real-Time Scheduling for Programmable DSPs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(1): 241-247 (2002) - [j11]Takahiro Kumura, Masao Ikekawa, Makoto Yoshida, Ichiro Kuroda:
VLIW DSP for mobile applications. IEEE Signal Process. Mag. 19(4): 10-21 (2002) - 2001
- [j10]Liang-Gee Chen, Hsueh-Ming Hang, Ichiro Kuroda:
Guest Editors' Introduction. J. VLSI Signal Process. 29(3): 155-156 (2001) - [j9]Tatsuji Moriyoshi, Hiroshi Shinohara, Takashi Miyazaki, Ichiro Kuroda:
Real-Time Software Video Codec with a Fast Adaptive Motion Vector Search. J. VLSI Signal Process. 29(3): 239-245 (2001) - [j8]Yuichiro Takamizawa, Kouhei Nadehara, Max Boegli, Masao Ikekawa, Ichiro Kuroda:
MPEG-2 AAC 5.1-Channel Decoder Software for a Low-Power Embedded RISC Microprocessor. J. VLSI Signal Process. 29(3): 247-254 (2001) - [c14]Takahiro Kumura, Daiji Ishii, Masao Ikekawa, Ichiro Kuroda, Makoto Yoshida:
A low-power programmable DSP core architecture for 3G mobile terminals. ICASSP 2001: 1017-1020 - [c13]Masao Ikekawa, M. Hori, Kouhei Nadehara, Takahiro Kumura, Makoto Yoshida, Ichiro Kuroda, Takao Nishitani:
Multimedia Signal Processor For Mobile Applications. ICME 2001 - 2000
- [j7]Leilei Song, Keshab K. Parhi
, Ichiro Kuroda, Takao Nishitani:
Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs. IEEE Trans. Very Large Scale Integr. Syst. 8(2): 160-172 (2000)
1990 – 1999
- 1999
- [j6]Kazumasa Suzuki, Masayuki Daito, Tomoo Inoue, Kouhei Nadehara, Masahiro Nomura, Masayuki Mizuno, Tomofumi Iima, Shoichiro Sato, Terumi Fukuda, Tomohisa Arai, Ichiro Kuroda, Masakazu Yamashina:
A 2000-MOPS embedded RISC processor with a Rambus DRAM controller. IEEE J. Solid State Circuits 34(7): 1010-1021 (1999) - [c12]Kouhei Nadehara, Takashi Miyazaki, Ichiro Kuroda:
Radix-4 FFT implementation using SIMD multimedia instructions. ICASSP 1999: 2131-2134 - 1998
- [j5]Hiroyuki Igura, Yukihiro Naito, Kenya Kazama, Ichiro Kuroda, Masato Motomura
, Masakazu Yamashina:
An 800-MOPS, 110-mW, 1.5-V, parallel DSP for mobile multimedia processing. IEEE J. Solid State Circuits 33(11): 1820-1828 (1998) - [j4]Kazumasa Suzuki, Tomohisa Arai, Kouhei Nadehara, Ichiro Kuroda:
V830R/AV: embedded multimedia superscalar RISC processor. IEEE Micro 18(2): 36-47 (1998) - [j3]Ichiro Kuroda, Takao Nishitani:
Multimedia processors. Proc. IEEE 86(6): 1203-1221 (1998) - [c11]Yukihiro Naito, Ichiro Kuroda:
H.263 mobile video codec based on a low power consumption digital signal processor. ICASSP 1998: 3041-3044 - [c10]Leilei Song, Keshab K. Parhi
, Ichiro Kuroda, Takao Nishitani:
Low-energy heterogeneous digit-serial Reed-Solomon codecs. ICASSP 1998: 3049-3052 - [c9]Eri Murata, Masao Ikekawa, Ichiro Kuroda:
Fast 2D IDCT implementation with multimedia instructions for a software MPEG2 decoder. ICASSP 1998: 3105-3108 - [c8]Kouhei Nadehara, Hanno Lieske, Ichiro Kuroda:
Software MPEG-2 video decoder on a 200-MHz, low-power multimedia microprocessor. ICASSP 1998: 3141-3144 - 1997
- [c7]Hans-Joachim Stolberg, Masao Ikekawa, Ichiro Kuroda:
Code positioning to reduce instruction cache misses in signal processing applications on multimedia RISC processors. ICASSP 1997: 699-702 - 1996
- [c6]Yukihiro Naito, Takashi Miyazaki, Ichiro Kuroda:
A fast full-search motion estimation method for programmable processors with a multiply-accumulator. ICASSP 1996: 3221-3224 - 1995
- [j2]Kouhei Nadehara, Ichiro Kuroda, Masayuki Daito, Takashi Nakayama:
Low-power multimedia RISC. IEEE Micro 15(6): 20-29 (1995) - 1992
- [c5]Jacob Levison, Ichiro Kuroda, Takao Nishitani:
A reconfigurable processor array with routing LSIs and general purpose DSPs. ASAP 1992: 102-116 - [c4]Ichiro Kuroda, Takao Nishitani:
Asynchronous multirate system design for programmable DSPs. ICASSP 1992: 549-552
1980 – 1989
- 1987
- [j1]Takao Nishitani, Ichiro Kuroda, Masao Satoh, Tadaharu Katoh, Yasuo Aoki:
A CCITT standard 32 kbit/s ADPCM LSI codec. IEEE Trans. Acoust. Speech Signal Process. 35(2): 219-225 (1987) - [c3]Ichiro Kuroda, Takao Nishitani, Teiji Takeuchi, Hitoshi Koyama, Junko Sunaga, Shuji Matsukawa:
Blockdiagram programming system for 32 bit floating point signal processor. ICASSP 1987: 1922-1925 - 1986
- [c2]Takao Nishitani, Ichiro Kuroda, Yuichi Kawakami, H. Tanaka, Tom Nukiyama:
Advanced single-chip signal processor. ICASSP 1986: 409-412 - 1985
- [c1]Takao Nishitani, Ichiro Kuroda, Masao Satoh, Tadaharu Katoh, Reiichi Fukuda, Yasushi Aoki:
A CCITT standard 32 kbps ADPCM LSI codec. ICASSP 1985: 1425-1428
Coauthor Index
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