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2020 – today
- 2022
[j4]Yusang Chun, Mohamed Megahed
, Ashwin Ramachandran, Tejasvi Anand:
A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS. IEEE J. Solid State Circuits 57(5): 1527-1541 (2022)- 2020
- [j3]Ashwin Ramachandran, Yusang Chun, Mohamed Megahed, Tejasvi Anand:
An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for Compensating Up To 27-dB Loss While Operating at 0.5-to-0.9 V and 3-to-16 Gb/s in 65-nm CMOS. IEEE J. Solid State Circuits 55(7): 1946-1959 (2020)
2010 – 2019
- 2019
- [j2]Ashwin Ramachandran, Arun Natarajan, Tejasvi Anand:
Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(3): 1192-1204 (2019) - [j1]Abhishekh Devaraj, Mohamed Megahed, Yutao Liu, Ashwin Ramachandran, Tejasvi Anand:
A Switched Capacitor Multiple Input Single Output Energy Harvester (Solar + Piezo) Achieving 74.6% Efficiency With Simultaneous MPPT. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(12): 4876-4887 (2019) - [c4]Yusang Chun, Ashwin Ramachandran, Tejasvi Anand:
A PAM-8 Wireline Transceiver with Receiver Side PWM (Time-Domain) Feed Forward Equalization Operating from 12-to-39.6Gb/s in 65nm CMOS. ESSCIRC 2019: 269-272 - 2018
- [c3]Ashwin Ramachandran, Tejasvi Anand:
A 0.5-to-0.9V, 3-to-16Gb/s, 1.6-to-3.1pJ/b wireline transceiver equalizing 27dB loss at 10Gb/s with clock-domain encoding using integrated pulse-width modulation (iPWM) in 65nm CMOS. ISSCC 2018: 268-270 - 2017
- [c2]Ashwin Ramachandran, Arun Natarajan, Tejasvi Anand:
29.4 A 16Gb/s 3.6pJ/b wireline transceiver with phase domain equalization scheme: Integrated pulse width modulation (iPWM) in 65nm CMOS. ISSCC 2017: 488-489
2000 – 2009
- 2005
- [c1]Ashwin Ramachandran, R. Michael Young:
Providing intelligent help across applications in dynamic user and environment contexts. IUI 2005: 269-271
Coauthor Index
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