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Jan Hlavicka
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2000 – 2009
- 2004
- [j9]Stanislav Racek, Pavel Herout, Jan Hlavicka:
Dependability Evaluation of Time Triggered Architecture Using Simulation. Comput. Artif. Intell. 23(1): 51-76 (2004) - 2003
- [j8]Jan Hlavicka, Petr Fiser:
BOOM - A Heuristic Boolean Minimizer. Comput. Artif. Intell. 22(1): 19-51 (2003) - [c12]Petr Fiser
, Jan Hlavicka, Hana Kubátová:
FC-Min: A Fast Multi-Output Boolean Minimizer. DSD 2003: 451-454 - 2002
- [j7]Khaled Elshafey, Jan Hlavicka:
Fault-Tolerant FPGA-Based Systems. Comput. Artif. Intell. 21(5) (2002) - [c11]Jan Hlavicka, Petr Fiser:
Minimization and Partitioning Method Reducing Input Sets. DELTA 2002: 434-436 - [c10]Jan Hlavicka, Stanislav Racek:
C-Sim - The C Language Enhancement for Discrete-Time Simulations. DSN 2002: 539 - [c9]Pavel Herout, Stanislav Racek, Jan Hlavicka:
Model-Based Dependability Evaluation Method for TTP/C Based Systems. EDCC 2002: 271-282 - [c8]Astrit Ademaj, Petr Grillinger, Pavel Herout, Jan Hlavicka:
Fault Tolerance Evaluation Using Two Software Based Fault Injection Methods. IOLTW 2002: 21-25 - 2001
- [c7]Petr Fiser
, Jan Hlavicka:
On the Use of Mutations in Boolean Minimization. DSD 2001: 300-309 - [c6]Jan Hlavicka, Petr Fiser
:
BOOM - A Heuristic Boolean Minimizer. ICCAD 2001: 439-442 - 2000
- [j6]Jan Hlavicka, Stanislav Racek, Pavel Herout:
Evaluation of process controller fault tolerance using simulation. Simul. Pract. Theory 7(8): 769-790 (2000) - [c5]Zdenek Kotásek, Richard Ruzicka, Jan Hlavicka:
Formal Approach to the RTL Testability Analysis. LATW 2000: 256-261
1990 – 1999
- 1999
- [e1]Jan Hlavicka, Erik Maehle, András Pataricza:
Dependable Computing - EDCC-3, Third European Dependable Computing Conference, Prague, Czech Republic, September 15-17, 1999, Proceedings. Lecture Notes in Computer Science 1667, Springer 1999, ISBN 3-540-66483-1 [contents] - 1997
- [j5]Jan Blatný, Zdenek Kotásek, Jan Hlavicka:
RT Level Test Scheduling. Comput. Artif. Intell. 16(1): 13-29 (1997) - 1996
- [j4]Yervant Zorian, Jan Hlavicka:
Guest Editors' Introduction: East Meets West. IEEE Des. Test Comput. 13(1): 5-7 (1996) - [c4]Jan Hlavicka, Stanislav Racek, Pavel Smrha:
Functional Validation of Fault-Tolerant Asynchronous Algorithms. EUROMICRO 1996: 143-150 - 1994
- [c3]Jan Hlavicka:
Position Paper. EDCC 1994: 411 - 1991
- [c2]Jan Hlavicka:
On the Complexity of System-Level Diagnosis Algorithms. EUROCAST 1991: 352-364
1980 – 1989
- 1989
- [c1]Jan Hlavicka:
Validation and Verification of Hardware and Software (Position Statement). IFIP Congress 1989: 343 - 1988
- [j3]P. Golan, Ondrej Novák, Jan Hlavicka:
Pseudoexhaustive Test Pattern Generator with Enhanced Fault Coverage. IEEE Trans. Computers 37(4): 496-500 (1988)
1970 – 1979
- 1973
- [j2]Jan Hlavicka:
Automatische Belegung von Flachbaugruppen im System PENTA-3. Elektron. Rechenanlagen 15(1): 25-28 (1973) - 1970
- [j1]Jan Hlavicka:
Essential Hazard Correction Without the Use of Delay Elements. IEEE Trans. Computers 19(3): 232-238 (1970)
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