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ORCIDYoung-Deuk Jeon
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2020 – today
- 2023
[c12]Youngsu Kwon, Jinho Han, Yong Cheol Peter Cho, Juyeob Kim, Jaehoon Chung, Jaewoong Choi, Sujin Park, Igyeong Kim, Hyunjeong Kwon, Jinkyu Kim, Hyunmi Kim, Won Jeon, Young-Deuk Jeon, Min-Hyung Cho, Minseok Choi:
Chiplet Heterogeneous-Integration AI Processor. ICEIC 2023: 1-2- [c11]Sujin Park, Yi-Gyeong Kim, Young-Deuk Jeon, Min-Hyung Cho, Jinho Han, Youngsu Kwon:
2.5D Large-Scale Interposer Bonding Process Verification using Daisy-Chain for PIM Heterogeneous Integration Platform. ICEIC 2023: 1-3 - [c10]Sujin Park, Young-Deuk Jeon, Yi-Gyeong Kim, Min-Hyung Cho, Jinho Han, Jaehoon Chung, Jaewoong Choi, Youngsu Kwon:
DQ and DQS Receiver for HBM3 Memory Interface with DFE Offset Calibration. ISOCC 2023: 215-216
2010 – 2019
- 2019
- [c9]Ki-Hyuk Park, Min-Hyung Cho, Young-Deuk Jeon, Joo Hyun Lee:
Design of Analog and Digital Hybrid MAC Circuit for Artificial Neural Networks. ICEIC 2019: 1-3 - 2012
- [j5]Young-Deuk Jeon, Jae-Won Nam
, Kwi-Dong Kim, Tae Moon Roh, Jong-Kee Kwon:
A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash-SAR Architecture. IEEE Trans. Circuits Syst. II Express Briefs 59-II(11): 741-745 (2012) - 2011
- [j4]Jae-Won Nam, Young-Deuk Jeon, Young-Kyun Cho, Jong-Kee Kwon:
A 12-bit 200-MS/s pipelined A/D converter with sampling skew reduction technique. Microelectron. J. 42(11): 1225-1230 (2011) - [j3]Young-Kyun Cho, Young-Deuk Jeon, Jae-Won Nam, Jong-Kee Kwon:
A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications. Microelectron. J. 42(12): 1335-1342 (2011) - [c8]Jae-Won Nam, Young-Deuk Jeon, Seok-Ju Yun, Tae Moon Roh, Jong-Kee Kwon:
A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS. ISOCC 2011: 405-407 - 2010
- [j2]Young-Kyun Cho, Young-Deuk Jeon, Jae-Won Nam, Jong-Kee Kwon:
A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique. IEEE Trans. Circuits Syst. II Express Briefs 57-II(7): 502-506 (2010) - [c7]Young-Deuk Jeon, Young-Kyun Cho, Jae-Won Nam, Kwi-Dong Kim, Woo-Yol Lee, Kuk-Tae Hong, Jong-Kee Kwon:
A 9.15mW 0.22mm2 10b 204MS/s pipelined SAR ADC in 65nm CMOS. CICC 2010: 1-4
2000 – 2009
- 2009
- [c6]Jae-Won Nam, Young-Deuk Jeon, Young-Kyun Cho, Sang-Gug Lee, Jong-Kee Kwon:
A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS. ESSCIRC 2009: 468-471 - 2007
- [j1]Seung-Chul Lee, Young-Deuk Jeon, Jong-Kee Kwon, Jongdae Kim:
A 10-bit 205-MS/s 1.0-mm2 90-nm CMOS Pipeline ADC for Flat Panel Display Applications. IEEE J. Solid State Circuits 42(12): 2688-2695 (2007) - [c5]Young-Deuk Jeon, Seung-Chul Lee, Kwi-Dong Kim, Jong-Kee Kwon, Jongdae Kim:
A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOS. ISSCC 2007: 456-615 - [c4]Seung-Chul Lee, Young-Deuk Jeon, Kwi-Dong Kim, Jong-Kee Kwon, Jongdae Kim, Jeong-Woong Moon, Woo-Yol Lee:
A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications. ISSCC 2007: 458-615 - 2006
- [c3]Young-Jae Cho, Doo-Hwan Sa, Yong-Woo Kim, Kyung-Hoon Lee, Hee-Cheol Choi, Seung-Hoon Lee, Young-Deuk Jeon, Seung-Chul Lee, Jong-Kee Kwon:
A 10b 25MS/s 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting Applications. CICC 2006: 497-500 - 2000
- [c2]Young-Deuk Jeon, Byeong-Lyeol Jeon, Seung-Chul Lee, Sang-Min Yoo, Seung-Hoon Lee:
A 12b 50 MHz 3.3V CMOS acquisition time minimized A/D converter. ASP-DAC 2000: 613-616 - [c1]Young-Deuk Jeon, Seung-Chul Lee, Sang-Min Yoo, Seung-Hoon Lee:
Acquisition-time minimization and merged-capacitor switching techniques for sampling-rate and resolution improvement of CMOS ADCs. ISCAS 2000: 451-454
Coauthor Index
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