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ORCIDISOCC 2023: Jeju, Republic of Korea
- 20th International SoC Design Conference, ISOCC 2023, Jeju, Republic of Korea, October 25-28, 2023. IEEE 2023, ISBN 979-8-3503-2703-8
- Younwoo Yoo, Hayoung Lee, Seung Ho Shin, Sungho Kang:
GPU-Based Redundancy Analysis using Partitioning Method for Memory Repair. 1-2 - Junhyuk Baik, Donghui Lee, Yongtae Kim:
A Smith-Waterman Hardware Accelerator Design using Sliding Window for Genomic Sequence Alignment. 1-2 - Aarthy Mani, Leong Xu Heng Victor, Anh Tuan Do:
Cryogenic Characterization of 40nm CMOS for Quantum Control Applications. 3-4 - Chiang Liang Kok, Zheng Yuan Loo, Jian Ping Chai:
Embedded Solutions for IoT Based Automated Drug Infusion Device. 5-6 - Donghui Lee, Junhyuk Baik, Yongtae Kim:
Enhancing Stochastic Computing using a Novel Hybrid Random Number Generator Integrating LFSR and Halton Sequence. 7-8 - Jaeeun Jeong, Jungeun Park, Woong Choi:
Improved Accuracy of Stochastic Accumulator Using Low-Cost Bitonic Sorter. 9-10 - Ji Won Kim, Jeong Seop Lee, Kang Yoon Lee:
A COT-based Highly Efficient Hybrid 3-Level Buck Converter for Next-Generation Memory Module Designs. 11-12 - Daisuke Ito, Yasuhiro Takahashi
, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS. 13-14 - Zayyir Ulric Cornelio, Paolo Resurreccion, Maria Theresa G. de Leon, Marc D. Rosales, John Richard E. Hizon:
An EEG Analog Front-End Unit for Wearable Applications Implemented in 28nm FD-SOI. 15-16 - Tsung-Wen Sun, Chu-En Hsia, Tsung-Heng Tsai, Chia-Chan Chang:
A 94.3 % Peak Power Efficiency Time-Based Buck Converter Using Pulse-Phase-Shift Modes with An Intrinsic Window for Transient Enhancement. 17-18 - Gwangmyeong An, Juneho Yoon, Taeho Kim, Hyunsu Jang, Myeongju Park, Bongsu Kim, Jongchan An, Junyoung Song:
A Digital LDO with Adaptive Loop Control and Reset-Voltage Optimization for Comparator. 19-20 - Seongyeon Yu, Namwook Hur, Wansun Kim, Mann-Ho Cho, Hyunchul Sohn, Joonki Suh, Hongsik Jeong, Jong-Hyeok Yoon:
A PRAM-based PIM Macro Using the Gilbert Multiplier-based Active Feedback and Input-aware SAR ADC. 21-22 - Shurun Li, Jie Liang, Liuyang Zhang:
An Automatic Offset Compensation Sense Amplifier Featuring High Readout Reliability for SRAM. 23-24 - Man-Jae Yang, Goen Hoe Kim, Kang-Yoon Lee:
A Small Area Cyclic Vernier Delay Line TDC Based ADDLL using Linear Delay Inverter. 25-26 - JunHa Lee, Kang-Yoon Lee:
Time Controlled Pre-Emphasis Circuit for Broadband Frequency Operation up to 3.6 Gbps. 27-28 - Nayeon Kim, Kwangrae Kim, Ki-Seok Chung:
Alert Refresh System for Mitigating RowHammer. 29-30 - Jeongeun Song, Sunyoung Lee, Minseok Shin, Ohjun Kwon, Hansang Kim, Yujin Park, Gyubeom Hwang, Hyekyoung Jung, Hoesam Jeong, Changrock Song, Woo-Seok Choi:
A Pixel Driver Design Technique to Obtain a High-Quality Depth Map in Indirect Time-of-Flight Sensors. 31-32 - Yongseung Lee, Donghun Kim, Jongsun Kim:
A GaN Driver IC With a TDC-Based Dead-Time Controller For GaN DC-DC Buck Converters. 33-34 - Kim-Hoang Nguyen, Woojin Ahn, Minkyu Je, Quyet Nguyen, Quynh-Trang Nguyen, Thanh-Tung Vu, Loan Pham-Nguyen:
A Neural Stimulator IC with Dynamic Voltage Scaling Supply and Energy Recycling for Cochlear Implant in Standard 180nm CMOS Process. 35-36 - Yunam Jin, Ayeon Gwon, Minseo Kim, Jiwoo Noh, Woong Choi, Junwon Jeong:
A Dynamic Power Transistor-Based CL-LDO with Wide Load Range and -53 dB PSRR Improvement. 37-38 - Tzung-Je Lee, Hung-Hsiang Chang, Chien-Hsiang Chao:
High Bandwidth Efficiency FPGA-based Underwater Acoustic Transceiver with Adaptive-SFDR DDFS. 39-40 - Daiki Hozumi, Shota Uchino, Takuji Kousaka, Hiroyuki Asahara:
Experimental Verification of Slow-Scale Oscillation in DC-DC Converter with Photovoltaic Module. 41-42 - Christian A. Cortes, Jan Paolo S. Cortez, Juhaina Angela Q. Custodia, Kevin Mathew D. Reyes, Mariane D. Sta. Barbara, Maria Theresa Gusad de Leon, John Richard E. Hizon, Marc D. Rosales:
10 Gb/s Energy-efficient Optical Transceiver using 1060 nm HCG MEMS-tunable VCSEL in 28 nm FD-SOI Technology. 43-44 - Hyeongjun Kim, Taegun Yim, Choong Keun Lee, Hongil Yoon:
A picowatt CMOS voltage reference with 0.046 %/V line sensitivity for a low-power IoT system. 45-46 - Sejin Park, Youngchang Choi, Seokhyeong Kang:
Soft Actor-Critic Reinforcement Learning-Based Optimization for Analog Circuit Sizing. 47-48 - Tzung-Je Lee, Yin-Wen Lo:
Temperature Sensor with 292.3 nA/°C Sensitivity Using Double Current Subtraction. 49-50 - Yogesh Verma, Mattis Hasler:
Crosstalk-Based Hardware Trojan In Low Power Designs. 51-52 - Friedrich Pauls, Sebastian Haas, Mattis Hasler:
Trust-minimized Integration of Third-Party Intellectual Property Cores. 53-54 - Nilanjana Das, Mattis Hasler, Sebastian Haas:
Implicit Hardware Trojan: Principles and Enabling Methods. 55-56 - Ryoma Katsube, Tomoaki Ukezono:
Investigation for Impact of Environmental Noise on Power Analysis Attacks. 57-58 - Minsu Park, Kang Yoon Lee:
Low Phase Noise Voltage-Controlled Oscillator with Self-Biased Negative-Gm Cell for IoT Applications. 61-62 - Heiner Bauer, Marco Stolba, Stefan Scholze, Dennis Walter, Christian Mayr, Alexander Oefelein, Sebastian Höppner, André Scharfe, Florian Schraut, Holger Eisenreich:
A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI. 67-68 - Yixuan He, Minsu Choi, Kyung-Ki Kim, Yong-Bin Kim:
Low-Power Counters using Pathfinding Technique. 69-70 - Mattis Hasler, Sebastian Haas:
Mitigating Message Passing Interference in Trusted Embedded Platforms. 71-72 - Yu-Heng Du, Bing-Feng Wu, Yuan-Hao Huang:
Tensor Compressive Sensing Processor for 64x64 Terahertz Single-Pixel Imaging. 73-74 - Hiroyuki Hama, Tomoaki Ukezono, Toshinori Sato:
Leveraging Approximate Computing for IoT Image Transmission. 75-76 - Toshinori Sato, Hiroyuki Hama, Tomoaki Ukezono:
Comparative Evaluation between Carry Prediction and Sign Error Correction in Approximate Addition. 77-78 - Shu-Chi Wang, Ching-Yuan Yang:
Behavior Simulation of CDR for SSC System With a Compact Quarter-Rate Linear Phase Detector. 79-80 - Wan-Yu You, Ching-Yuan Yang:
Behavior Simulation of SSC Generator With Adjustable Modulation Frequency and Depth. 81-82 - Seong Jae Eom, Eui-Young Chung:
Adaptive Tag Comparison for Hybrid Cache. 83-84 - Syam Sankar, Lissiyas Antony, Ruchika Gupta, John Jose, Sukumar Nandi:
Exploring Trustable Paths in Network-on-Chip for Low-Slack Packets. 85-86 - Hyoju Seo, Seokhyeon Lee, Yongtae Kim:
Computation Exactness Exploration of Exact Quantum Adders in NISQ. 87-88 - Seong-Bo Park, Jun-Ho Boo, Jae-Geun Lim, Hyoung-Jung Kim, Jae-Hyuk Lee, Won-Jun Cho, Gil-Cho Ahn:
A Second-Order DT Delta-Sigma Modulator with Noise-Shaping SAR Quantizer. 89-90 - Hou-Hsuan Lin, Jia-Fong Shih, Yung-Hui Chung:
A 90-dB DR Discrete-Time Delta-Sigma Modulator for Audio Applications. 91-92 - Chan Kuen Sim, Aarthy Mani, Anh Tuan Do:
0.85 mW, 8-bit, 1GS/s, 58dB SFDR Cryogenic DAC for Superconducting Qubit Control Applications. 93-94 - Tzung-Je Lee, Kuo-Hsun Tu:
10-bit 250-KS/s M-2M Digital-to-Analog Converter with 4-4-2 Segmentation for Sonar System. 95-96 - Gyubin Seong, Jong Kang Park, Jong Tae Kim:
FPGA Implementation of Cycle-Reduced Diagonal Data Flow Systolic Array for Edge Device AI. 99-100 - Hyunsoo Lee, Hyundong Lee, Minseung Shin, Gyuri Shin, Sumin Jeon, Taigon Song:
High-throughput PIM (Processing in-Memory) for DRAM using Bank-level Pipelined Architecture. 101-102 - Yen-Ching Chang, Szu-Ting Wang, Ying-Hsiu Hung, Yao-Feng Liang, Ming-Hwa Sheu, Shin-Chi Lai:
Heart Valve Disease Recognition Using Phonocardiogram Signal Based on A Lightweight Convolution Neural Network. 103-105 - Kei Palabasan, Ramona Rajagopalan, Jean-Marriz Manzano, Marc D. Rosales, Maria Theresa G. de Leon, John Richard E. Hizon:
Comparison of hardware-optimized CNN and SVM models for human activity recognition using the HARTH and HAR 70 + datasets. 107-108 - Sihan Kim, Changmin Song, Jinseok Kim, Yonghun Oh, Changwan Kim, Young-Chan Jang:
A 10-Gb/s Dual-Loop Reference-less CDR with FD Controller. 109-110 - Hyun-Bin Lee, Won-Young Lee:
An Anti-Harmonic-Lock Frequency Detector for Continuous-Rate Clock and Data Recovery. 111-112 - Jihee Kim, Woo-Seok Choi:
A Baud-Rate Clock and Data Recovery With Collaborative Maximum-Eye Tracking Method. 113-114 - Seoung-Geun Cho, Jin-Ku Kang:
A PAM-4 Baud-Rate CDR with High-Gain Phase Detector Using Shared Sampler. 115-116 - Youngmin Oh, Taeyang Sim, Jaeduk Han:
Analysis of Grounded Coplanar Waveguide (GCPW) for High-Speed Links Channel. 117-118 - MinSeung Shin, Jongbeom Kim, Yunjeong Shin, Taigon Song:
A Compact Q-Learning-Based Standard Cell Layout Compiler for 3nm GAAFET and Beyond. 119-120 - Jinmyoung Kim, Taewhan Kim:
Allocation of Multi-bit Flip-Flops Targeting Low-Power Chips. 121-122 - Chaehyun Kim, Taewhan Kim:
Maximizing Power Saving Through State-Driven Clock Gating. 123-124 - Junseok Hur, Jaekyung Im, Seokhyeong Kang:
Placement Initialization via Community Detection. 125-126 - Jisoo Lee, Daseul Moon, Woohyun Kim, Woong Choi:
Design and Analysis of Compound Gates for Lightweight Multiplier. 127-128 - Jihoon Jang, Heedo Jeong, Jaeduk Han:
Multi-Phase Frequency Divider Generator with Process-Independent Automation. 129-130 - Jihyeon Lee, Jaehoon Jeong, Hyungeun Kim, Jinho Jeong:
Design of Bessel-like filter-based ESD protection I/O pad with improved eye performance. 131-132 - Youngwon Cho, Jaehun Jeong, Jinwook Burm:
A 12-bit 5MS/s Synchronous SAR ADC With Comparator Using High Gain Pre-amplifier. 133-135 - Taegun Kim, Dong Keun Lee, Sihyun Kim, Sangwan Kim:
A simulation study about the memory operation of 3D-stacked capacitor-less 1T DRAM cells based on ferroelectric field-effect transistors (FeFETs). 135-136 - Nu Ri Kim, Suk-Ju Kang:
Optimized Image Quality Determination for Backlight Dimming. 137-138 - Hyoseok Song, Kwangmin Kim, Changyoon Han, Byungsub Kim:
Review: A Speculative Divide-and-Conquer Optimization Method for Large Analog/Mixed-Signal Circuits. 139-140 - Jihoon Jang, Hyun Kim, Hyokeun Lee:
A Spatio-Temporal Switchable Data Prefetcher for Convolutional Neural Networks. 141-142 - HaYoung Lim, Yeseo Jang, Juyeon Kim, Jaehyeong Sim:
TD-NAAS: Template-Based Differentiable Neural Architecture Accelerator Search. 143-144 - Young Woo Jeong, Won Sik Jeong, Jin Young Shin, Seung Eun Lee:
The Design of Embedded Fuzzy Logic Controller for Autonomous Mobile Robots. 145-146 - Beom Jin Kang, Nam Joon Kim, Jong Ho Lee, Hyun Kim:
Hardware-friendly Activation Functions for HybridViT Models. 147-148 - Subin Kim, Yunseon Choi, Byunghan Lee:
Considerations in Evaluation of Deep Hashing Networks for Information Retrieval System. 149-150 - Yu-Jeong Kim, Sung-Yoon Jung:
Experimental Assessment of 1D-DCT Based Display Field Communication Scheme. 151-153 - Nilesh Maharjan, Byung Wook Kim:
Pointing error effect in FSO satellite-to-ground under weak turbulence condition. 153-154 - Ren Izumi, Makoto Nakamura, Daisuke Ito:
Inductor-less CMOS TIA Based on MSTA for Low-power and Low-noise Optical Communication. 155-156 - Kazuki Shakuda, Zhengqiang Tang, Shintaro Arai:
Communication Performance Depending on LED Installation Position in Image Sensor Communication Using Propeller LED Transmitter. 157-158 - Shintaro Arai, Daisuke Ito:
Development of Propeller LED Transmitter for High-Speed Image Sensor Communication. 159-160 - Yuta Suzuki, Kaito Kato, Hiroyuki Asahara, Takuji Kousaka:
Bifurcation analysis of a chaotic interrupted system with a periodic threshold. 161-162 - Jiaying Lin, Ryuji Nagazawa, Kien Nguyen, Hiroo Sekiya, Hiroyuki Torikai, Mikio Hasegawa, Won-Joo Hwang:
Pavlovian Conditioning Modeling Using Wireless Spiking Neural Network. 163-164 - Akihiro Konishi, Ken Onodera, Yutaro Komiyama, Kien Nguyen, Hiroo Sekiya, Xiuqin Wei:
Load-Independent Multiple Output WPT System With Fixed Coupling Coils. 165-166 - Takuya Nakamura, Yoshifumi Nishio, Yoko Uwate:
Time Series Analysis with Three Types of Noise-Mixing Effects by Neural Network. 167-168 - Masaya Kudo, Hiroyuki Torikai:
A hardware-efficient wireless functional electrical stimulation system based on ergodic cellular automaton dynamics. 169-170 - Yun-Ting Zhang, Chin-Fu Nien, Chia-Wei Lin, Wen-Jui Chao, Chen-Yu Liu, Lien-Po Yu, Yuan-Ho Chen:
An Automated Toolchain for QUBO-based Optimization with Quantum-inspired Annealers. 171-172 - Song-Nien Tang, Yuan-Ho Chen, Yu-Wei Chang, Yu-Ting Chen, Shuo-Hung Chou:
Hybrid CNN-LSTM Network for ECG Classification and Its Software-Hardware Co-Design Approach. 173-174 - Chin Hsia, Chung-Yi Li, Deng-Fong Lu, Tzu-Yu Chen:
Integrated All-GaN Driver for High-voltage DC-DC Power Converters. 175-176 - En-Chi Yang, Suz-Ting Wang, Kusn-Lin Liu, Wen-Ho Juang, Ming-Hwa Sheu, How-Chiun Wu, Shin-Chi Lai:
Fast Measurement of Impedance Calculation for Electrochemical Impedance Spectroscopy. 177-178 - Chung-Yi Li, Tzu-Yu Chen, Deng-Fong Lu, Yue-Liang Chou, Hung-Chi Chen, Shinn-Yn Lin:
Robust Cascaded Boost Converter with See-Saw Stress-Relief Control. 179-180 - Ying-Hsiu Hung, Yen-Ching Chang, Suz-Ting Wang, Jeng-Dao Lee, Wen-Ho Juang, Ming-Hwa Sheu, Shin-Chi Lai:
Convolutional Neural Network-based Keyword Classification for Mixer Control. 181-182 - Gianfranco Avitabile, Roberto Cancelli, Antonello Florio, Ka Lok Man, Giuseppe Coviello:
A Simple Active Transponder for X-band SAR Satellite Applications. 183-184 - Tso-Bing Juang, Chun-Chi Fan, Guan-Zhong Lin:
Lower-Error and Area-Efficient Complex Divider Design using Logarithmic Number Systems (LNS). 185-186 - Gabriela Mogos:
Quantum Biometric Fingerprint Encryption based on Twofish Algorithm. 187-188 - Esun Baik, Hyo-Jin Park, Sung-Wan Hong:
A Capacitor-less LDO for Mobile Devices with Fast Transient Using High Gain Positive Feedback Loop. 189-190 - Mi-Ji Go, Jun-Ho Boo, Jae-Geun Lim, Hyoung-Jung Kim, Jae-Hyuk Lee, Seong-Bo Park, Byeongho Yu, Won-Jun Cho, Gil-Cho Ahn:
A 12-bit 3-MS/s Synchronous SAR ADC With a Hybrid RC DAC. 191-192 - J. Y. Li, G. X. Sun, Chun Zhao, Ka Lok Man, S. Lam, X. Tu:
Bioinspired Solution-processed Artificial Synaptic Thin-Film Transistor. 193-194 - Yu Du, Jeremy S. Smith, Ka Lok Man, Eng Gee Lim:
Image Radar Point Cloud Segmentation with Segment Anything Model. 195-196 - Yoko Uwate, Yoshifumi Nishio:
Feature Extraction of Neuron Group Composed of Two Different Firing Patterns Using Nonlinear Analysis. 199-200 - Seokjin Oh, Rina Yoon, Seungmyeong Cho, Kyeong-Sik Min:
Memristor Circuits for Non-Backpropagation Training Algorithm. 201 - Jerald Yoo:
Energy-Efficient AI at the edge for Biomedical Applications. 202 - Hyeonjin Jo, Chaerin Sim, Jaewoo Park, Jongeun Lee:
Accelerating Transformers with Fourier-Based Attention for Efficient On-Device Inference. 203-204 - Jeong-Mi Park, Jin-Ku Kang:
A PAM-4 Receiver with Selective Reference Voltage Adaptation for Low Sensitivity to Sampler Voltage Variations. 205-206 - Gwangeun Byeon, Seongwook Kim, Seokin Hong:
Improving Performance and Energy-efficiency of DNN Accelerators with STT-RAM Buffers. 207-208 - Chulwoo Lee, Hanyoung Lee, Phap Duong-Ngoc, Hanho Lee:
Twiddle Factor Generator Architecture for Number Theoretic Transform. 209-210 - Akshay Kumar Sharma, Kyung Ki Kim:
Optimizing Image Classification with Inverse Depthwise Separable Convolution for Edge Devices. 211-212 - Sujin Park, Young-Deuk Jeon, Yi-Gyeong Kim, Min-Hyung Cho, Jinho Han, Jaehoon Chung, Jaewoong Choi, Youngsu Kwon:
DQ and DQS Receiver for HBM3 Memory Interface with DFE Offset Calibration. 215-216 - Youngsu Kwon:
ABSX: The Chiplet Hyperscale AI Processing Unit for Energy-Efficient High-Performance AI Processing. 217-218 - Yong-Nam Koh, Ju-Hyung Kim, Soo-Jeong Kim, Ju-Hwan Jang, Jae-Sung Lim, Jayden Donghyun Kim:
Signal integrity analysis of heterogeneous integration using Si bridge technology. 221-222 - Park Jong-Kyung, Park Sang-Woo, Jeong Min-Seong:
Advancements in Metal Passivation Process for Low-Temperature Cu-Cu Direct Bonding. 223-224 - Shoma Sato, Hiroyuki Torikai:
Analyses of nonlinear transient phenomena of ergodic cellular automaton central pattern generator. 227-228 - Takahiro Hattori, Yoko Uwate, Yoshifumi Nishio:
Synchronization Phenomena of Two Coupled Chaotic Circuits Using Stochastic Coupling. 229-230 - Jumpei Kamitoko, Hiroyuki Torikai:
A chopper-type mixed gait controller based on ergodic cellular automaton central pattern generator. 231-232 - Haruka Sakohira, Kiichi Yamashita, Yoko Uwate, Yoshifumi Nishio:
Rewiring Effect of High Synchronization Edges in Complex Oscillator Networks. 233-234 - Daiki Akai, Kiichi Yamashita, Yoko Uwate, Yoshifumi Nishio:
Synchoronization Penomena of Coupled Oscillators in Weighted Three-Dimensional Complex Networks. 235-236 - Yuki Matsubara, Yuki Ishikawa, Yoko Uwate, Yoshifumi Nishio:
Effect of Lateral Connection on Synchronization Phenomena in Chaotic Circuits Coupled with Non-Uniform Coupling Strength. 237-238 - Yong-Cheng Liaw, Shuo-Han Chen, Hsin-Yun Su:
Lowering the Number of Live-Page Copies on Solid State Drives through Trim-Assisted Space Allocation. 239-240 - Yu-Shiang Tsai, Shuo-Han Chen, Yong-Cheng Liaw, Cheng-Yueh Wu:
Exploring Hot/Cold Data Separation for Garbage Collection Efficiency Enhancement on OCSSDs. 241-242 - Yi-Shen Chen, Ying-Jui Shih, Jen-Wei Hsieh:
Mitigating Write Amplification of Dual-mode Flash Memory. 243-244 - Lee Chang, Chien-Chung Ho, Tei-Wei Kuo:
Alleviating Deduplication-oriented Fragmentation of SSDs by Considering File Hotness and Popularity. 245-246 - Yi-Syuan Lin, Yu-Pei Liang, Yu-Shan Yen, Yen-Ting Chen, Wei-Kuan Shih, Yuan-Hao Chang:
Adaptive Mode-Switching for Write-amplification Reduction of SMR Disks. 247-248 - Jiwon Yoon, Hyunwoo Kim, Boogyo Sim, Hyunwook Park, Yi-Gyeong Kim, Sujin Park, Youngsu Kwon, Joungho Kim:
Multi-Stripline Redistribution Layer Interposer Channel Design for High Bandwidth Memory Module Considering Via Interconnect. 247-248 - Yi-Syuan Lin, Chin-Yu Lo, Yi-Chao Shih, Tseng-Yi Chen:
Alleviating the Impact of Fingerprint Operations on NAND Flash Memory Storage Performance. 249-250 - Yukinojo Kotani, Yoko Uwate, Yoshifumi Nishio:
Synchronizations in Three Coupled Oscillators with Memristor Synapses as Ring Structure. 251-252 - Yui Kishimoto, Hiroyuki Torikai:
A hardware-efficient FPGA cochlear model for next generation nonlinear cochlear implant. 253-255 - Kengo Hosoi, Hiroyuki Torikai:
A learnable network of analog electronic neuron models for brain prosthetic implant. 255-256 - Haruki Terakawa, Hideyuki Kato, Yoshihiro Yonemura, Yuichi Katori:
Analysis of predictive coding model with hierarchical reservoir computing for modeling Stroop effects. 257-258 - Kazuki Yasufuku, Yoko Uwate, Yoshifumi Nishio:
A Study of Changes in Prediction Performance Influenced by Attractor State in Oscillator Reservoir Computing. 259-260 - Jaehun Jeong, Jonghyuk Chae, Seungju Lee, Jinwook Burm:
A Compact Design of SPAD Detector with Quenching Circuit for Reduced Dark Count Rate. 261-262 - Jonghyuk Chae, Jaehun Jeong, Byeongha Park, Jinwook Burm:
A 8-bit DPWM-based Analog Bypass Circuit and System for LED Matrix Headlamp in High-Voltage 180-nm CMOS Technology. 263-264 - Jia Park, Woo-Seok Choi:
An Analog Integrate-and-Fire Neuron with Robust Soft Reset Mechanism. 265-266 - Adam Jefferson Ramones, Paolo Miguel Villacorta, Kyla Marie Juruena, Trixi Emmanuelle Obar, John Robert Siglos, Jean-Marriz Manzano, Zyrel Renzo Sanchez, Arcel G. Leynes, Maria Sophia Ralota, John Richard E. Hizon, Marc D. Rosales, Maria Theresa G. de Leon:
A 288nV/√Hz low-noise capacitively-coupled instrumentation amplifier (CCIA) in 22-nm UTBB FD-SOI for signal conditioning of MEMS piezoresistive pressure sensors. 267-268 - Kyla Marie Juruena, Paolo Miguel Villacorta, Trixi Emmanuelle Obar, John Robert Siglos, Adam Jefferson Ramones, Jean-Marriz Manzano, Zyrel Renzo Sanchez, Arcel G. Leynes, Maria Sophia Ralota, John Richard E. Hizon, Marc D. Rosales, Maria Theresa G. de Leon:
A high CMRR, high input impedance current-feedback instrumentation amplifier (CFIA) in 22-nm UTBB FD-SOI for signal conditioning of MEMS piezoresistive pressure sensors. 269-270 - Chau-Thao Cao, Pham Hong Bao Ngoc, Loan Pham-Nguyen, Xuan Thanh Pham:
A High Input Impedance Low Noise Amplifier Capable Of Handling 1V Electrode Offset for Biopotential Recording. 273-274 - Hee-Cheol Joo, Hyein Kim, Young-Ha Hwang:
A 0.4-VIN, External-Capacitor-Free, Adaptive-Biased LDO with Look-Ahead Droop Reduction for Wake-up Features in Edge Devices. 275-276 - Leanghok Hour, Myeongseong Go, Youngsun Han:
Preliminary Study on Reducing Memory Overhead in Accelerating Quantum Computer Simulations Using PIM Technology. 277-278 - Chun-Mao Chen, Jia-Ching Chuang, Hao-Li Liu:
FPGA-Controlled High-Power Driving Design for High Intensity Focused Ultrasound Application. 279-280 - Euigeun Kim, Jinwook Burm:
Electro-Optical Phase Locked Loop design for FMCW LiDAR TX in 28-nm CMOS. 281-282 - Jaewoong Ahn, Seung Hun Choi, Junyeol An, Hyung-Min Lee:
An Area-Efficient Column Driver with Fully Nonlinear Gamma Scale for Mobile AMOLEDs. 283-284 - Giussepe Yvanric Galvez, Andrew James Lim, Christopher Jr Camarillo, John Rey Marturillas, Mark Emannuel Teodoro, Ellris Kristian Nuel Urfano, Anastacia B. Alvarez, Ryan Albert G. Antonio, Fredrick Angelo R. Galapon, Sherry Joy Alvionne Baquiran, Allen Jason Tan, Lawrence Roman A. Quizon:
Integration of In-Memory Computing Capabilities to a Self-Matching Complementary-Reference Sensing Scheme for TST-MRAM. 285-286 - Sunghoon Kim, Donghyun Han, Seokjun Jang, Sungho Kang:
LOTS: Low Overhead TSV Repair Method Using IEEE-1838 Standard Architecture. 289-290 - Keerthana Pamidimukkala, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi:
Modeling Truncation-Based Approximation Error in Stochastic Computing Circuits. 291-292 - Go-Eun Woo, Sangbo Park, Hyungwon Kim:
Improving Performance of Current Sensor Chip Based on Multi-Parameter Compensation : Compensation & Decimation Filter for Digital Chip. 293-294 - Haewoon Son, WonSeok Yang, Hoyong Jung, Young-Chan Jang:
1-kS/s 12-bit SAR ADC with Burst Conversion. 295-296 - Hye-Min Shin, Hae-Won Son, Tai-Soon Park, Tae-Woo Oh, Young-Chan Jang:
First-order Continuous Time Delta-sigma Modulator with 3-bit SAR ADC and PNM DAC. 297-298 - Donghun Cho, Hyeseong Lee, Jeonghun Lee, Jaehee You:
HVS-based AR Display Image Enhancement With Delta Look-Up Table Considering Ambient Light. 299-300 - Yujin Lim, Dongwhee Kim, Jungrae Kim:
SCC: Efficient Error Correction Codes for MLC PCM. 303-304 - Wonyeong Jung, Dongwhee Kim, Jungrae Kim:
Synergistic Integration: An Optimal Combination of On-Die and Rank-Level ECC for Enhanced Reliability. 305-306 - Jaehyuk So, Dong Hyun Lee:
Design of Wafer Vision Alignment System using Hardware Simulator. 307-308 - Hojung Namkoong, Jungrae Kim:
CPR: Correlation-based Page Remapping. 309-310 - Sanghyun Kim, Eunchong Lee, Minkyu Lee, Kyungho Kim, Sang-Seol Lee, Sung-Joon Jang:
A Max Pooling Hardware Architecture Supporting Inference And Training For CNN Accelerators. 313-314 - Elim Lee, Youngmin Kim:
A Power-Efficient 10T D Flip-Flop with Dual Line of Four Switches using 65nm CMOS Technology. 315-316 - Jiwon Kim, Seungsik Moon, Youngjoo Lee:
Low-Complexity Phase Shift Design for IRS-Aided SU-MIMO Wireless Systems. 317-318 - Joungmin Park, Seongmo An, Jinyeol Kim, Seung Eun Lee:
Continuous Convolution Accelerator with Data Reuse based on Systolic Architecture. 319-320 - Kim Isaac I. Buelagala, Ginzy S. Javier, Sean Alfred A. Lipardo, James Carlo E. Sorsona, Sherry Joy Alvionne S. Baquiran, Lawrence Roman A. Quizon, Allen Jason Tan, Ryan Albert G. Antonio, Fredrick Angelo R. Galapon, Anastacia B. Alvarez:
Energy-Efficient Sparse Hyperdimensional Computing for Speech Recognition. 321-322 - Kyou-Jung Son, Seokhun Jeon, Jae-Hack Lee, Byung-Soo Kim:
Distance Searching-based Hyperparameter Optimization for Restricted Coulomb Energy-based Neural Network. 323-324 - Bogeun Jung, Geonhui Jang, Hyungwon Kim:
Enhancing Performance and Energy Efficiency of Reconfigurable CNN Accelerator. 327-328 - Amrita Rana, Kyung Ki Kim:
Efficient Object Detection through Migration-Based Neural Architecture Search. 329-330 - Sang-Bo Park, Dong-Yeong Lee, Hyungwon Kim:
Reconfigurable Cell-Based Systolic Array Architecture for CNN Training Accelerator for Mobile Applications. 331-332 - Gitae Park, Thaising Taing, Hyungwon Kim:
High-Speed FPGA-to-FPGA Interface for a Multi-Chip CNN Accelerator. 333-334 - Seunghyun Park, Dongkyu Lee, Daejin Park:
Tcl-based Simulation Platform for Light-weight ResNet Implementation. 335-336 - Taehoon Kim, Woo-Seok Choi:
Performance Comparison of Clocked Comparators Using Impulse Sensitivity Function. 337-338 - Hayoung Lee, Younwoo Yoo, Seung Ho Shin, Sungho Kang:
Redundancy Analysis Simplification Scheme for High-Speed Memory Repair. 339-340 - Hyojoon Yun, Tae-Hyun Kim, Sungho Kang:
Machine Learning based Scan Chain Diagnosis for Double Faults. 341-342 - Hyemin Kim, Sangjun Lee, Jongho Park, Sungwhan Park, Sungho Kang:
A New Flip-flop Shared Architecture of Test Point Insertion for Scan Design. 343-344 - Kihwan Jeon, Taewhan Kim:
Fast Refinement on Placement Legalization for Designs with Mixed-Height Cells. 345-346 - Ilseon Ha, Taewhan Kim:
Optimizing Timing for Multi-bit Flip-Flop Intensive Designs Compatible with Commercial EDA Flow. 347-348 - Donggyu Kim, Jakang Lee, Seokhyeong Kang:
Advanced Parasitic Capacitance Extraction using Active Learning. 349-350 - Hyeri Roh, Woo-Seok Choi:
Design of Energy-Efficient Cryptographically Secure Pseudo-Random Number Generators Using High-Level Synthesis. 351-352 - Jiwoo Nam, Daijoon Hyun:
Bayesian Optimization for Parameter Tuning in Placement-Aware Logic Synthesis. 353-354 - Bona Lim, Hanhee Jo, Jaeduk Han:
An Analysis of Current-mode Drivers in 40-nm CMOS Technology. 355-356
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