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2020 – today
- 2024
[j9]Kaniz Mishty, Mehdi Sadi
:
System and Design Technology Co-Optimization of SOT-MRAM for High-Performance AI Accelerator Memory System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(4): 1065-1078 (2024)- [i9]R. Alexander Knipper, Kaniz Mishty, Mehdi Sadi, Shubhra Kanti Karmaker Santu:
SNNLP: Energy-Efficient Natural Language Processing Using Spiking Neural Networks. CoRR abs/2401.17911 (2024) - [i8]Kaniz Mishty, Mehdi Sadi:
Chiplet-Gym: Optimizing Chiplet-based AI Accelerator Design with Reinforcement Learning. CoRR abs/2406.00858 (2024) - 2023
- [j8]Mehdi Sadi, Bashir Mohammad Sabquat Bahar Talukder, Kaniz Mishty, Md. Tauhidur Rahman:
Attacking Deep Learning AI Hardware with Universal Adversarial Perturbation. Inf. 14(9): 516 (2023) - [c14]Kaniz Mishty, Mehdi Sadi:
System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning. ACM Great Lakes Symposium on VLSI 2023: 697-702 - [i7]Kaniz Mishty, Mehdi Sadi:
System and Design Technology Co-optimization of SOT-MRAM for High-Performance AI Accelerator Memory System. CoRR abs/2303.12310 (2023) - 2022
- [j7]Mehdi Sadi, Ujjwal Guin:
Test and Yield Loss Reduction of AI and Deep Learning Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(1): 104-115 (2022) - [c13]R. Alexander Knipper, Md. Mahadi Hassan, Mehdi Sadi, Shubhra Kanti Karmaker Santu:
Analogy-Guided Evolutionary Pretraining of Binary Word Embeddings. AACL/IJCNLP (1) 2022: 683-693 - [c12]Mehdi Sadi, Yi He, Yanjing Li, Mahabubul Alam, Satwik Kundu, Swaroop Ghosh, Javad Bahrami, Naghmeh Karimi:
Special Session: On the Reliability of Conventional and Quantum Neural Network Hardware. VTS 2022: 1-12 - 2021
- [j6]Kaniz Mishty, Mehdi Sadi:
Designing Efficient and High-Performance AI Accelerators With Customized STT-MRAM. IEEE Trans. Very Large Scale Integr. Syst. 29(10): 1730-1742 (2021) - [c11]Farah Ferdaus, Bashir M. Sabquat Bahar Talukder, Mehdi Sadi, Md. Tauhidur Rahman:
True Random Number Generation using Latency Variations of Commercial MRAM Chips. ISQED 2021: 510-515 - [c10]Shamik Kundu, Kanad Basu, Mehdi Sadi, Twisha Titirsha, Shihao Song, Anup Das, Ujjwal Guin:
Special Session: Reliability Analysis for AI/ML Hardware. VTS 2021: 1-10 - [i6]Shamik Kundu, Kanad Basu, Mehdi Sadi, Twisha Titirsha, Shihao Song, Anup Das, Ujjwal Guin:
Special Session: Reliability Analysis for ML/AI Hardware. CoRR abs/2103.12166 (2021) - [i5]Farah Ferdaus, Bashir M. Sabquat Bahar Talukder, Mehdi Sadi, Md. Tauhidur Rahman:
True Random Number Generation using Latency Variations of Commercial MRAM Chips. CoRR abs/2104.00198 (2021) - [i4]Kaniz Mishty, Mehdi Sadi:
Designing Efficient and High-performance AI Accelerators with Customized STT-MRAM. CoRR abs/2104.02199 (2021) - [i3]Mehdi Sadi, Bashir M. Sabquat Bahar Talukder, Kaniz Mishty, Md. Tauhidur Rahman:
Attacking Deep Learning AI Hardware with Universal Adversarial Perturbation. CoRR abs/2111.09488 (2021) - 2020
- [j5]Md. Mahbub Alam, Adib Nahiyan, Mehdi Sadi, Domenic Forte, Mark M. Tehranipoor:
Soft-HaT: Software-Based Silicon Reprogramming for Hardware Trojan Implementation. ACM Trans. Design Autom. Electr. Syst. 25(4): 35:1-35:22 (2020) - [i2]Mehdi Sadi, Ujjwal Guin:
Yield Loss Reduction and Test of AI and Deep Learning Accelerators. CoRR abs/2006.04798 (2020)
2010 – 2019
- 2018
- [i1]Adib Nahiyan, Mehdi Sadi, Rahul Vittal, Gustavo K. Contreras, Domenic Forte, Mark M. Tehranipoor:
Hardware Trojan Detection through Information Flow Security Verification. CoRR abs/1803.04102 (2018) - 2017
- [j4]Mehdi Sadi, Sukeshwar Kannan, LeRoy Winemberg, Mark M. Tehranipoor:
SoC Speed Binning Using Machine Learning and On-Chip Slack Sensors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(5): 842-854 (2017) - [j3]Xiaoxiao Wang, Pengyuan Jiao, Mehdi Sadi, Donglin Su, LeRoy Winemberg, Mark M. Tehranipoor:
TRO: An On-Chip Ring Oscillator-Based GHz Transient IR-Drop Monitor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(5): 855-868 (2017) - [j2]Mehdi Sadi, Gustavo K. Contreras, Jifeng Chen, LeRoy Winemberg, Mark M. Tehranipoor:
Design of Reliable SoCs With BIST Hardware and Machine Learning. IEEE Trans. Very Large Scale Integr. Syst. 25(11): 3237-3250 (2017) - [c9]Mehdi Sadi, Sukeshwar Kannan, Luke England, Mark M. Tehranipoor:
Design of a digital IP for 3D-IC die-to-die clock synchronization. ISCAS 2017: 1-4 - [c8]Adib Nahiyan, Mehdi Sadi, Rahul Vittal, Gustavo K. Contreras, Domenic Forte, Mark M. Tehranipoor:
Hardware trojan detection through information flow security verification. ITC 2017: 1-10 - 2016
- [j1]Mehdi Sadi, Mark M. Tehranipoor:
Design of a Network of Digital Sensor Macros for Extracting Power Supply Noise Profile in SoCs. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1702-1714 (2016) - [c7]Sukeshwar Kannan, Mehdi Sadi, Luke England:
Power delivery in 3D packages: current crowding effects, dynamic IR drop and compensation network using sensors (invited paper). ICCAD 2016: 55 - [c6]Liting Yu, Xiaoxiao Wang, Yuanqing Cheng, Xiaoying Zhao, Pengyuan Jiao, Aixin Chen, Donglin Su, LeRoy Winemberg, Mehdi Sadi, Mark M. Tehranipoor:
An efficient all-digital IR-Drop Alarmer for DVFS-based SoC. ISCAS 2016: 221-224 - [c5]Mehdi Sadi, Gustavo K. Contreras, Dat Tran, Jifeng Chen, LeRoy Winemberg, Mark M. Tehranipoor:
BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learning. ITC 2016: 1-10 - 2015
- [c4]Mehdi Sadi, Mark M. Tehranipoor, Xiaoxiao Wang, LeRoy Winemberg:
Speed Binning Using Machine Learning And On-chip Slack Sensors. ACM Great Lakes Symposium on VLSI 2015: 155-160 - [c3]Mehdi Sadi, LeRoy Winemberg, Mark M. Tehranipoor:
A robust digital sensor IP and sensor insertion flow for in-situ path timing slack monitoring in SoCs. VTS 2015: 1-6 - 2014
- [c2]Mehdi Sadi, Zoe Conroy, Bill Eklow, Matthias Kamm, Nematollah Bidokhti, Mark Mohammad Tehranipoor:
An All Digital Distributed Sensor Network Based Framework for Continuous Noise Monitoring and Timing Failure Analysis in SoCs. ATS 2014: 269-274 - 2012
- [c1]Mehdi Sadi, Mircea Stan:
Design of near threshold All Digital Delay Locked Loops. SoCC 2012: 137-142
Coauthor Index
aka: Mark Mohammad Tehranipoor
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last updated on 2024-10-07 21:16 CEST by the dblp team
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