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Jiarui Liu 0001
Person information
- affiliation (PhD 2014): Zhejiang University, School of Aeronautics and Astronautics, Hangzhou, China
Other persons with the same name
- Jiarui Liu (aka: Jia-Rui Liu) — disambiguation page
- Jiarui Liu 0002
— Sun Yat-sen University, School of Computer Science and Engineering, Guangzhou, China
- Jiarui Liu 0003 — Chinese Academy of Sciences, Institute of Automation, Beijing, China (and 1 more)
- Jiarui Liu 0004 — Carnegie Mellon University, PA, USA (and 1 more)
- Jiarui Liu 0005
— North China Electric Power University, School of Control and Computer Engineering, Beijing, China
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2020 – today
- 2023
- [j17]Xiaoye Peng
, Faxin Yu, Zhiyu Wang
, Jiarui Liu
, Chenge Wang, Jing Wang:
A Frequency-Domain I/Q Imbalance Calibration Algorithm for Wideband Direct Conversion Receivers Using Low-Cost Compensator. IEEE Access 11: 48739-48748 (2023) - [j16]Yantian Xu, Zhiyu Wang, Jiarui Liu, Hua Chen, Faxin Yu:
Multi-chip phase synchronization circuit of fractional-N PLL. IEICE Electron. Express 20(9): 20230035 (2023) - [j15]Yaguang Song, Yilun Wang, Jiarui Liu, Hua Chen, Faxin Yu:
A 0.1-1.9GHz 65nm CMOS variable-gain mixer-first receiver with DSA and noise-shaping TIA. IEICE Electron. Express 20(9): 20230086 (2023) - [j14]Guojing Huang, Zhiyu Wang, Jiarui Liu, Hua Chen, Faxin Yu:
An enhanced peak limited digital predistortion based on indirect learning architecture. IEICE Electron. Express 20(19): 20230358 (2023) - 2022
- [j13]Yu Liu, Mingliang Chen, Chenge Wang, Jiarui Liu, Zhiyu Wang, Hua Chen, Faxin Yu:
A parasitic elimination bootstrapped switch and a fast settling residual amplifier for high-speed and high-resolution pipelined ADC. IEICE Electron. Express 19(15): 20220084 (2022) - [j12]Fengjie Wang
, Zhiyu Wang
, Jiarui Liu, Faxin Yu:
A 14-Bit 3-GS/s DAC Achieving SFDR >63dB Up to 1.4GHz With Random Differential-Quad Switching Technique. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 879-883 (2022) - [j11]Faxin Yu, Jiahao Chen
, Haoming Li, Tengjia Wang, Yao Yang
, Wenfang Xiong, Zhiyu Wang
, Jiarui Liu
:
A Low Phase Noise VCO With Placement Reordered Cores and High-Q Bond Wire Array Inductors. IEEE Trans. Circuits Syst. II Express Briefs 69(9): 3754-3758 (2022) - 2021
- [j10]Jiahao Chen, Haoming Li, Tengjia Wang, Zhiyu Wang, Hua Chen, Jiarui Liu, Faxin Yu:
A 92 fsrms jitter frequency synthesizer based on a multicore class-C voltage-controlled oscillator with digital automatic amplitude control. IEICE Electron. Express 18(10): 20210136 (2021) - [j9]Mingliang Chen, Keke Wu, Yupeng Shen, Zhiyu Wang, Hua Chen, Jiarui Liu, Faxin Yu:
A 14bit 500MS/s 85.62dBc SFDR 66.29dB SNDR SHA-less pipelined ADC with a stable and high-linearity input buffer and aperture-error calibration in 40nm CMOS. IEICE Electron. Express 18(11): 20210171 (2021) - 2020
- [j8]Tengjia Wang, Min Zhou, Jiarui Liu, Zhiyu Wang, Jiongjiong Mo, Hua Chen, Faxin Yu:
A highly linear 10 Gb/s MOS current mode logic driver with large output voltage swing based on an active inductor. IEICE Electron. Express 17(11): 20200160 (2020)
2010 – 2019
- 2019
- [j7]Yupeng Shen, Haoming Li, Xubin Chen, Jiarui Liu, Hua Chen:
A 0.07-3 GHz wideband front-end for SDR receiver with 2.3 dB NF and 12 dBm IIP3 in 65 nm CMOS. IEICE Electron. Express 16(4): 20181089 (2019) - [j6]Xubin Chen, Xuan Li, Yupeng Shen, Jiarui Liu, Hua Chen:
A 14 bit 500 MS/s SHA-less pipelined ADC with a highly linear input buffer and power-efficient supply voltage domain arrangement in 40 nm CMOS. IEICE Electron. Express 16(11): 20190197 (2019) - [j5]Fengjie Wang, Liyi Fan, Yupeng Shen, Hua Chen, Jiarui Liu, Zhiyu Wang, Fa-Xin Yu:
An effective DC offset calibration method combined with analog and digital circuits for direct conversion receivers. IEICE Electron. Express 16(19): 20190518 (2019) - [j4]Haoming Li, Yupeng Shen, Tengjia Wang, Jiarui Liu:
A 210fs RMS jitter 187.5 MHz-3GHz fractional-N frequency synthesizer with quantization noise suppression techniques and chopping differential charge pump for SDR applications. Microelectron. J. 85: 135-143 (2019) - 2018
- [j3]Gang Wang, Wei Chen, Jiarui Liu, Jiongjiong Mo, Hua Chen, Zhiyu Wang, Fa-Xin Yu:
Design of a broadband Ka-band MMIC LNA using deep negative feedback loop. IEICE Electron. Express 15(10): 20180317 (2018) - 2017
- [j2]Jinpeng Qiu, Tong Liu, Xubin Chen, Yong-Heng Shang
, Jiongjiong Mo
, Zhiyu Wang, Hua Chen
, Jiarui Liu, Jingjing Lv, Fa-Xin Yu:
A New Digital to Analog Converter Based on Low-Offset Bandgap Reference. J. Electr. Comput. Eng. 2017: 1658695:1-1658695:10 (2017) - 2013
- [j1]Jia-Rui Liu, Shize Guo, Zhe-Ming Lu, Fa-Xin Yu, Hui Li:
An Approximate Flow Betweenness Centrality Measure for Complex Network. IEICE Trans. Inf. Syst. 96-D(3): 727-730 (2013)
Coauthor Index
aka: Fa-Xin Yu
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last updated on 2024-08-22 19:43 CEST by the dblp team
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