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2010 – 2019
- 2018
[j3]Xinfeng Xie
, Dayou Du, Qian Li, Yun Liang, Wai Teng Tang, Zhongliang Ong, Mian Lu, Huynh Phung Huynh, Rick Siow Mong Goh:
Exploiting Sparsity to Accelerate Fully Connected Layers of CNN-Based Applications on Mobile SoCs. ACM Trans. Embed. Comput. Syst. 17(2): 37:1-37:25 (2018)- 2015
- [j2]Mian Lu, Yun Liang, Huynh Phung Huynh, Zhongliang Ong, Bingsheng He, Rick Siow Mong Goh:
MrPhi: An Optimized MapReduce Framework on Intel Xeon Phi Coprocessors. IEEE Trans. Parallel Distributed Syst. 26(11): 3066-3078 (2015) - 2014
- [j1]Huynh Phung Huynh, Andrei Hagiescu, Zhong-Liang Ong, Weng-Fai Wong, Rick Siow Mong Goh:
Mapping Streaming Applications onto GPU Systems. IEEE Trans. Parallel Distributed Syst. 25(9): 2374-2385 (2014) - [c3]Jianxing Wang, Yenni Tim, Weng-Fai Wong, Zhong-Liang Ong, Zhenyu Sun, Hai Li:
A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores. ASP-DAC 2014: 610-615 - 2013
- [c2]Mian Lu, Lei Zhang, Huynh Phung Huynh, Zhongliang Ong, Yun Liang, Bingsheng He, Rick Siow Mong Goh, Richard Huynh:
Optimizing the MapReduce framework on Intel Xeon Phi coprocessor. IEEE BigData 2013: 125-130 - [i1]Mian Lu, Lei Zhang, Huynh Phung Huynh, Zhongliang Ong, Yun Liang, Bingsheng He, Rick Siow Mong Goh, Richard Huynh:
Optimizing the MapReduce Framework on Intel Xeon Phi Coprocessor. CoRR abs/1309.0215 (2013) - 2011
- [c1]Zhenyu Sun, Xiuyuan Bi, Hai (Helen) Li, Weng-Fai Wong, Zhong-Liang Ong, Xiaochun Zhu, Wenqing Wu:
Multi retention level STT-RAM cache designs with a dynamic refresh scheme. MICRO 2011: 329-338
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