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ORCIDAbhishek Nag
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2020 – today
- 2023
[j9]Vivek Kumar Singh
, Abhishek Nag, Abhishek Bhattacharjee, Sambhu Nath Pradhan:
Design and Lifetime Estimation of Low-Power 6-Input Look-Up Table Used in Modern FPGA. J. Circuits Syst. Comput. 32(7): 2350113:1-2350113:19 (2023)- 2022
- [j8]Abhishek Bhattacharjee, Abhishek Nag, Kaushik Das, Sambhu Nath Pradhan:
Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation. J. Electron. Test. 38(1): 91-105 (2022) - [j7]Vivek Kumar Singh, Abhishek Nag, Sambhu Nath Pradhan:
Design and analysis of a low power strategy in finite state machines implemented in configurable logic blocks. Int. J. Embed. Syst. 15(4): 326-332 (2022) - 2020
- [j6]Abhishek Nag, Subhajit Das, Sambhu Nath Pradhan:
Low power transistor level synthesis of finite state machines using a novel dual gating technique. Int. J. Embed. Syst. 13(4): 431-438 (2020)
2010 – 2019
- 2019
- [j5]Abhishek Nag, Subhajit Das, Sambhu Nath Pradhan:
Low-Power FSM Synthesis Based on Automated Power and Clock Gating Technique. J. Circuits Syst. Comput. 28(5): 1920003:1-1920003:20 (2019) - 2017
- [j4]Abhishek Nag, Debanjali Nath, Sambhu Nath Pradhan:
Leakage Reduction of SRAM-Based Look-Up Table Using Dynamic Power Gating. J. Circuits Syst. Comput. 26(3): 1750041:1-1750041:12 (2017) - 2016
- [j3]Abhishek Nag, Sambhu Nath Pradhan:
An Autonomous Clock Gating Technique in Finite State Machines Based on Registers Partitioning. J. Circuits Syst. Comput. 25(5): 1650033:1-1650033:21 (2016) - 2015
- [j2]Sambhu Nath Pradhan, Angshuman Chakraborty, Abhishek Nag, Debanjali Nath:
Layout-oriented look up table-based dual threshold approach to reduce leakage. Int. J. Comput. Aided Eng. Technol. 7(4): 456-480 (2015) - 2014
- [j1]Debanjali Nath, Priyanka Choudhury, Abhishek Nag, Sambhu Nath Pradhan:
Power gating architecture implementation inside clock period to reduce power. Int. J. Comput. Aided Eng. Technol. 6(3): 310-323 (2014)
Coauthor Index
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