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ORCIDSambhu Nath Pradhan
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2020 – today
- 2023
[j31]Kaushik Das
, Sambhu Nath Pradhan:
Hardware architecture design for complementary ensemble empirical mode decomposition algorithm. Integr. 91: 153-164 (2023)- [j30]Vivek Kumar Singh, Abhishek Nag, Abhishek Bhattacharjee, Sambhu Nath Pradhan:
Design and Lifetime Estimation of Low-Power 6-Input Look-Up Table Used in Modern FPGA. J. Circuits Syst. Comput. 32(7): 2350113:1-2350113:19 (2023) - 2022
- [j29]Abhishek Bhattacharjee, Abhishek Nag, Kaushik Das, Sambhu Nath Pradhan:
Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation. J. Electron. Test. 38(1): 91-105 (2022) - [j28]Apangshu Das, Vivek Kumar Singh, Sambhu Nath Pradhan:
Shared reduced ordered binary decision diagram-based thermal-aware network synthesis. Int. J. Circuit Theory Appl. 50(6): 2271-2286 (2022) - [j27]Vivek Kumar Singh, Abhishek Nag, Sambhu Nath Pradhan:
Design and analysis of a low power strategy in finite state machines implemented in configurable logic blocks. Int. J. Embed. Syst. 15(4): 326-332 (2022) - 2021
- [j26]Abhishek Bhattacharjee, Dheeraj Kumar Sahu, Sambhu Nath Pradhan:
Lookup table-based negative-bias temperature instability effect and leakage power co-optimization using genetic algorithm approach. Int. J. Circuit Theory Appl. 49(7): 1902-1915 (2021) - [j25]Kaushik Das, Sambhu Nath Pradhan:
Field-programmable gate array-based design for real-time computation of ensemble empirical mode decomposition. Int. J. Circuit Theory Appl. 49(8): 2312-2328 (2021) - [j24]Abhishek Bhattacharjee, Sambhu Nath Pradhan:
NBTI-Aware Power Gating Design with Dynamically Varying Stress Probability Control on Sleep Transistor. J. Circuits Syst. Comput. 30(11): 2120004:1-2120004:21 (2021) - [j23]Koel Datta Purkayastha, Ritesh Kishore Mishra, Arunava Shil, Sambhu Nath Pradhan:
IoT Based Design of Air Quality Monitoring System Web Server for Android Platform. Wirel. Pers. Commun. 118(4): 2921-2940 (2021) - 2020
- [j22]Somnath Roy Choudhury, Sambhu Nath Pradhan:
An Improved Matrix Generation Framework for Thermal Aware Placement in VLSI. IEEE Access 8: 216365-216385 (2020) - [j21]Kaushik Das, Debanjali Nath, Sambhu Nath Pradhan:
FPGA and ASIC realisation of EMD algorithm for real-time signal processing. IET Circuits Devices Syst. 14(6): 741-749 (2020) - [j20]Kaushik Das, Sambhu Nath Pradhan:
An efficient hardware realization of EMD for real-time signal processing applications. Int. J. Circuit Theory Appl. 48(12): 2202-2218 (2020) - [j19]Abhishek Nag, Subhajit Das, Sambhu Nath Pradhan:
Low power transistor level synthesis of finite state machines using a novel dual gating technique. Int. J. Embed. Syst. 13(4): 431-438 (2020) - [j18]Apangshu Das, Sambhu Nath Pradhan:
An Elitist Non-Dominated Multi-Objective Genetic Algorithm Based Temperature Aware Circuit Synthesis. Int. J. Interact. Multim. Artif. Intell. 6(4): 26-38 (2020) - [j17]Apangshu Das, Yallapragada C. Hareesh, Sambhu Nath Pradhan:
NSGA-II Based Thermal-Aware Mixed Polarity Dual Reed-Muller Network Synthesis Using Parallel Tabular Technique. J. Circuits Syst. Comput. 29(15): 2020008:1-2020008:23 (2020)
2010 – 2019
- 2019
- [j16]Somnath Roy Choudhury, Sambhu Nath Pradhan:
DOTFloor-A Diffusion Oriented Time-Improved Floorplanner for Macrocells. IEEE Access 7: 172074-172087 (2019) - [j15]Abhishek Nag, Subhajit Das, Sambhu Nath Pradhan:
Low-Power FSM Synthesis Based on Automated Power and Clock Gating Technique. J. Circuits Syst. Comput. 28(5): 1920003:1-1920003:20 (2019) - [j14]Priyanka Choudhury, Kanchan Manna, Vivek Rai, Sambhu Nath Pradhan:
Thermal-Aware Partitioning and Encoding of Power-Gated FSM. J. Circuits Syst. Comput. 28(9): 1950144:1-1950144:14 (2019) - 2018
- [j13]Ashim Saha, Sambhu Nath Pradhan:
Facial expression recognition based on eigenspaces and principle component analysis. Int. J. Comput. Vis. Robotics 8(2): 190-200 (2018) - 2017
- [j12]Sambhu Nath Pradhan, Priyanka Choudhury, Debanjali Nath:
Transistor level realisation of power gated FSM. Int. J. Comput. Aided Eng. Technol. 9(3): 351-371 (2017) - [j11]Abhishek Nag, Debanjali Nath, Sambhu Nath Pradhan:
Leakage Reduction of SRAM-Based Look-Up Table Using Dynamic Power Gating. J. Circuits Syst. Comput. 26(3): 1750041:1-1750041:12 (2017) - 2016
- [j10]Abhishek Nag, Sambhu Nath Pradhan:
An Autonomous Clock Gating Technique in Finite State Machines Based on Registers Partitioning. J. Circuits Syst. Comput. 25(5): 1650033:1-1650033:21 (2016) - [j9]Debanjali Nath, Priyanka Choudhury, Sambhu Nath Pradhan:
Hybrid Approach of Within-Clock Power Gating and Normal Power Gating to Reduce Power. J. Circuits Syst. Comput. 25(5): 1650044:1-1650044:26 (2016) - [j8]Apangshu Das, Sambhu Nath Pradhan:
Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits. VLSI Design 2016: 3191286:1-3191286:14 (2016) - 2015
- [j7]Sambhu Nath Pradhan, Angshuman Chakraborty, Abhishek Nag, Debanjali Nath:
Layout-oriented look up table-based dual threshold approach to reduce leakage. Int. J. Comput. Aided Eng. Technol. 7(4): 456-480 (2015) - [c9]Apangshu Das, Sambhu Nath Pradhan:
Thermal aware FPRM based AND-XOR network synthesis of logic circuits. ReTIS 2015: 497-502 - [c8]Priyanka Choudhury, Debanjali Nath, Vivek Rai, Sambhu Nath Pradhan:
Thermal aware AND-OR-XOR network synthesis. VDAT 2015: 1-6 - 2014
- [j6]Debanjali Nath, Priyanka Choudhury, Abhishek Nag, Sambhu Nath Pradhan:
Power gating architecture implementation inside clock period to reduce power. Int. J. Comput. Aided Eng. Technol. 6(3): 310-323 (2014) - 2013
- [j5]Angshuman Chakraborty, Sambhu Nath Pradhan:
Gate level leakage minimisation at 90 nm technology. Int. J. Comput. Aided Eng. Technol. 5(4): 375-386 (2013) - [c7]Debanjali Nath, Priyanka Choudhury, Sambhu Nath Pradhan:
Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG). VDAT 2013: 160-168 - 2012
- [j4]Sambhu Nath Pradhan, Santanu Chattopadhyay:
Multiplexer-Based Multi-Level Circuit Synthesis with Area-Power Trade-Off. J. Circuits Syst. Comput. 21(5) (2012) - [j3]Priyanka Choudhury, Sambhu Nath Pradhan:
An Approach for Low Power Design of Power Gated Finite State Machines Considering Partitioning and State Encoding Together. J. Low Power Electron. 8(4): 452-463 (2012) - [c6]Angshuman Chakraborty, Sambhu Nath Pradhan:
A technique for power reduction of CMOS circuit at 65nm technology. RAIT 2012: 576-580 - [c5]Priyanka Choudhury, Sambhu Nath Pradhan:
Power Modeling of Power Gated FSM and Its Low Power Realization by Simultaneous Partitioning and State Encoding Using Genetic Algorithm. VDAT 2012: 19-29 - 2011
- [j2]Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay:
Low power finite state machine synthesis using power-gating. Integr. 44(3): 175-184 (2011) - [j1]Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay:
And-or-XOR Network Synthesis with Area-Power Trade-Off. J. Circuits Syst. Comput. 20(6): 1019-1035 (2011)
2000 – 2009
- 2008
- [c4]Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay:
Three-level AND-OR-XOR network synthesis: A GA based approach. APCCAS 2008: 574-577 - [c3]Sambhu Nath Pradhan, Santanu Chattopadhyay:
AND-XOR Network Synthesis with Area-Power Trade-off. ICIIS 2008: 1-6 - [c2]Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay:
Integrated Power-Gating and State Assignment for Low Power FSM Synthesis. ISVLSI 2008: 269-274 - 2006
- [c1]Gopal Paul, Sambhu Nath Pradhan, Ajit Pal, Bhargab B. Bhattacharya:
Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic. APCCAS 2006: 1504-1507
Coauthor Index
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