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ORCIDKyung-Sub Son
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- affiliation: Inha University, Incheon, South Korea
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2020 – today
- 2020
[j10]Kyung-Sub Son
, Taek-Joon An, Yong-Hwan Moon, Jin-Ku Kang:
A 0.42-3.45 Gb/s Referenceless Clock and Data Recovery Circuit With Counter-Based Unrestricted Frequency Acquisition. IEEE Trans. Circuits Syst. II Express Briefs 67-II(6): 974-978 (2020)
2010 – 2019
- 2019
- [j9]Seong-Mun An, Kyung-Sub Son, Taek-Joon An, Jin-Ku Kang:
Design of a third-order delta-sigma TDC with error-feedback structure. IEICE Electron. Express 16(3): 20181064 (2019) - [j8]Kyung-Sub Son, Yong-Hwan Moon, Sanghun Baek, Namyong Kim, Taek-Joon An, Jin-Ku Kang:
Eye-open monitor using two-dimensional counter value profile. IEICE Electron. Express 16(21): 20190601 (2019) - [j7]Yong-Hwan Moon, Jae-Wook Yoo, Young-Soo Ryu, Sang-Ho Kim, Kyung-Sub Son, Jin-Ku Kang:
A 2.41-pJ/bit 5.4-Gb/s Dual-Loop Reference-Less CDR With Fully Digital Quarter-Rate Linear Phase Detector for Embedded DisplayPort. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(8): 2907-2920 (2019) - 2018
- [c5]Min Kim, Kyung-Sub Son, Namhoon Kim, Chang Hang Rho, Jin-Ku Kang:
A Two-Step Time-to-Digital Converter using Ring Oscillator Time Amplifier. ISOCC 2018: 143-144 - 2017
- [j6]Nguyen Huu Tho, Kyung-Sub Son, Jin-Ku Kang:
A 200 Mb/s∼3.2 Gb/s referenceless clock and data recovery circuit with bidirectional frequency detector. IEICE Electron. Express 14(8): 20161279 (2017) - 2016
- [j5]Bum-Hee Choi, Kyung-Sub Son, Taek-Joon An, Jin-Ku Kang:
A burst-mode clock and data recovery circuit with two symmetric quadrature VCO's. IEICE Electron. Express 13(24): 20161086 (2016) - [c4]Bum-Hee Choi, Kyung-Sub Son, Jin-Ku Kang:
A low jitter burst-mode clock and data recovery circuit with two symmetric VCO's. APCCAS 2016: 344-347 - [c3]Nguyen Huu Tho, Kyung-Sub Son, Kyongsu Lee, Jin-Ku Kang:
A 200-Mb/s to 3-Gb/s wide-band referenceless CDR using bidirectional frequency detector. ISOCC 2016: 259-260 - 2015
- [j4]Kyung-Sub Son, Jin-Ku Kang:
On-chip jitter tolerance measurement technique with independent jitter frequency modulation from VCO in CDR. IEICE Electron. Express 12(15): 20150570 (2015) - [j3]In-Seok Kong, Kyung-Sub Son, Kyongsu Lee, Jin-Ku Kang:
Precise time-difference repetition for TDC with delay mismatch cancelling scheme. IEICE Electron. Express 12(21): 20150752 (2015) - [c2]Kyung-Sub Son, Kyongsu Lee, Jin-Ku Kang:
On-chip jitter tolerance measurement technique for CDR circuits. ISCAS 2015: 1602-1605 - 2014
- [j2]Taek-Joon Ahn, Kyung-Sub Son, Yong-Sung Ahn, Jin-Ku Kang:
A low-power CDR using dynamic CML latches and V/I converter merged with XOR for half-rate linear phase detection. IEICE Electron. Express 11(17): 20140657 (2014) - [j1]Kyongsu Lee, Youngjin Kim, Kyung-Sub Son, Sangmin Lee, Jin-Ku Kang:
A 1.1 mW/Gb/s 10 Gbps half-rate clock-embedded transceiver for high-speed links in 65 nm CMOS. IEICE Electron. Express 11(17): 20140671 (2014) - [c1]Taek-Joon An, Kyung-Sub Son, Young-Jin Kim, In-Seok Kong, Jin-Ku Kang:
A 8.7mW 5-Gb/s clock and data recovery circuit with 0.18-µm CMOS. ISCAS 2014: 2329-2332
Coauthor Index
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