"A 8.7mW 5-Gb/s clock and data recovery circuit with 0.18-µm CMOS."

Taek-Joon An et al. (2014)

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DOI: 10.1109/ISCAS.2014.6865638

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Taek-Joon An, Kyung-Sub Son, Young-Jin Kim, In-Seok Kong, Jin-Ku Kang:
A 8.7mW 5-Gb/s clock and data recovery circuit with 0.18-µm CMOS. ISCAS 2014: 2329-2332

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