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Cheng Li 0010
Person information
- affiliation: University of California, Davis, CA, USA
- affiliation (former): University of Macau, State Key Laboratory of Analog and Mixed-Signal VLSI, Macau
Other persons with the same name
- Cheng Li — disambiguation page
- Cheng Li 0001 — University of Science and Technology of China (USTC), China (and 1 more)
- Cheng Li 0002 — Hong Kong University of Science and Technology, Department of Electronic and Computer Engineering, Clear Water Bay, Hong Kong
- Cheng Li 0003 — Deakin University, Center for Pattern Recognition and Data Analytics (PRaDA), Geelong, Australia
- Cheng Li 0004 — Shanghai Jiao Tong University, Department of Electronic Engineering, Institute of Wireless Communications Technology, China
- Cheng Li 0005 — Memorial University of Newfoundland, Department of Electrical and Computer Engineering, St. John's, NL, Canada
- Cheng Li 0006 — College of William and Mary, Department of Computer Science, Williamsburg, VA, USA
- Cheng Li 0007 — Beihang University, School of Instrumentation Science and Opto-electronics Engineering, Beijing, China
- Cheng Li 0008 — Chinese Academy of Sciences, Shenzhen Institutes of Advanced Technology, Paul C. Lauterbur Research Center for Biomedical Imaging, China
- Cheng Li 0009 — SenseTime Research, Beijing, China (and 1 more)
- Cheng Li 0011 — University of Rochester, Department of Electrical and Computer Engineering, NY, USA (and 1 more)
- Cheng Li 0012 — Google, Mountain View, CA, USA (and 1 more)
- Cheng Li 0013 — University of Kent, UK
- Cheng Li 0014 — University of Illinois Urbana-Champaign, IL, USA
- Cheng Li 0015 — Harbin Institute of Technology, Department of Control Science and Engineering, China (and 1 more)
- Cheng Li 0016 — Peking University, Center For Biolnformatics, Beijing, China (and 3 more)
- Cheng Li 0017 — Xidian University, Institute of Intelligent Control and Image Engineering, Xi'an, China
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2020 – today
- 2023
- [j5]Hamidreza Afzal, Cheng Li, Omeed Momeni:
A Highly Efficient 165-GHz 4FSK 17-Gb/s Transceiver System With Frequency Overlapping Architecture in 65-nm CMOS. IEEE J. Solid State Circuits 58(11): 3113-3126 (2023)
2010 – 2019
- 2019
- [j4]Cheng Li, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins:
Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(1): 82-93 (2019) - 2018
- [j3]Yan Zhu, Chi-Hang Chan, Zi-Hao Zheng, Cheng Li, Jianyu Zhong, Rui Paulo Martins:
A 0.19 mm2 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3606-3616 (2018) - [j2]Guan-Cheng Wang, Cheng Li, Yan Zhu, Jianyu Zhong, Yan Lu, Chi-Hang Chan, Rui Paulo Martins:
Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3707-3719 (2018) - 2017
- [j1]Chi-Hang Chan, Yan Zhu, Cheng Li, Wai-Hong Zhang, Iok-Meng Ho, Lai Wei, Seng-Pan U, Rui Paulo Martins:
60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration. IEEE J. Solid State Circuits 52(10): 2576-2588 (2017)
Coauthor Index
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