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Alexandre Ayres De Sousa

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2010 – 2019

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2017
[c2]
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  dblp key:
  - conf/essderc/Fenouillet-Beranger17
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  - https://dblp.org/rec/conf/essderc/Fenouillet-Beranger17
Claire Fenouillet-Béranger, S. Beaurepaire, Fabien Deprat, Alexandre Ayres De Sousa, Laurent Brunet, Perrine Batude, Olivier Rozeau, François Andrieu, Paul Besombes, M.-P. Samson, Bernard Previtali, F. Nemouchi, G. Rodriguez, Philippe Rodriguez, R. Famulok, Nils Rambal, Viorel Balan, Z. Saghi, V. Jousseaume, Charles-Antoine Guérin, F. Ibars, F. Proud, D. Nouguier, David Ney, V. Delaye, H. Dansas, X. Federspiel, Maud Vinet:
Guidelines for intermediate back end of line (BEOL) for 3D sequential integration. ESSDERC 2017: 252-255
2015
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Hossam Sarhan, Sébastien Thuries, Olivier Billoint, Fabien Deprat, Alexandre Ayres De Sousa, Perrine Batude, Claire Fenouillet-Béranger, Fabien Clermidy:
Intermediate BEOL process influence on power and performance for 3DVLSI. 3DIC 2015: TS1.3.1-TS1.3.5

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