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2020 – today

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2021
[c3]
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  dblp key:
  - conf/isqed/Sankaranarayanan21
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Rajsaktish Sankaranarayanan, Archanna Srinivasan, Arch Zaliznyak, Sreelekha Mittai:
Chip Package Co-design and Physical Verification for Heterogeneous Integration. ISQED 2021: 275-279

2000 – 2009

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2005
[c2]
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  - conf/cicc/VenkataCTLNKNZX05
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Ramanand Venkata, Vinson Chan, Binh Ton, Chong Lee, Huy Ngo, Malik Kabani, Tam Nguyen, Arch Zaliznyak, Ning Xue, Steven Shen, Michael Zheng, Michael Lai, Steve Park, Lana Chan, Divya Vijayaraghavan, John Lam, Rakesh H. Patel:
Multi-protocol embedded PCS IP in a FPGA-SOC. CICC 2005: 783-786

1990 – 1999

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1999
[c1]
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  - conf/cicc/SasakiBCCMMKTRZ99
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Paul T. Sasaki, Yogendra Bobra, Warren E. Cory, Atul V. Cihia, Suresh M, Menon, Madhavi Kola, Mammen Thomas, Prasad Rau, Arch Zaliznyak:
A fast, predictable FPGA with PLLs, dual port SRAMs and active repeaters. CICC 1999: 179-182

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