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2020 – today
- 2024
[c6]M. Kang, M. Chang, Y. Park, C. Noh, S. H. Hong, B. Park, Y. H. Park, Y. C. Jung, W. S. Lim, G. H. Kim, Y. Lee, H. Yang, D. Shin, J. G. Yang, K. H. Cho, W. C. Jeong, H.-J. Cho, Wook-Hyeon Kwon, D. W. Kim, K. Rim, J. H. Song:
Device Design and Reliability of GAA MBCFET. IRPS 2024: 1-6- [c5]H. Fukutome, J. Kim, J. Shin, J. Kim, Y. Lee, Y. Park, D. Oh, S. Chae, B. Eom, YS Nam, M. Lee, S. Ha, EG Chung, J. Kim, M. Jo, SH Lee, S. Kim, KH Cho, KW Lee, DW Kim, HJ Cho, K. Rim, SD Kwon, J. Song:
Demonstration of Logic-Block Performance-Power Gain by 1st Generation Back Side Power Delivery Network for SoC and HPC Applications Beyond 2nm Node. VLSI Technology and Circuits 2024: 1-2 - 2022
- [c4]H. Fukutome, K. Suh, W. Kim, Y. Moriyama, S. Kang, B. Eom, J. Kim, C. Yoon, W. Kwon, Y. Chung, Y. Nam, Y. Kim, S. Park, J. Park, H.-J. Cho, K. Rim, S. D. Kwon:
Comprehensive Feasibility Study of Single FIN Transistors for Scaling Both Switching Energy and Device Footprint. VLSI Technology and Circuits 2022: 369-370
2010 – 2019
- 2016
- [c3]Seung Chul Song, J. Xu, D. Yang, K. Rim, P. Feng, Jerry Bao, J. Zhu, Joseph Wang, G. Nallapati, Mustafa Badaroglu, Praneeth Narayanasetti, B. Bucki, Jeff Fischer, Geoffrey Yeap:
Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes. VLSI Circuits 2016: 1-2 - 2015
- [c2]N. N. Mojumder, Seung Chul Song, K. Rim, J. Xu, Joseph Wang, J. Zhu, Milena Vratonjic, K. Lin, Martin Saint-Laurent, Paul Bassett, Geoffrey Yeap:
Transistor-interconnect mobile system-on-chip co-design method for holistic battery energy minimization. VLSIC 2015: 84- - [c1]Seung Chul Song, J. Xu, N. N. Mojumder, K. Rim, D. Yang, Jerry Bao, J. Zhu, Joseph Wang, Mustafa Badaroglu, V. Machkaoutsan, Praneeth Narayanasetti, B. Bucki, Jeff Fischer, Geoffrey Yeap:
Holistic technology optimization and key enablers for 7nm mobile SoC. VLSIC 2015: 198-
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