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Anugerah Firdauzi
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2010 – 2019
- 2019
- [j2]Zule Xu, Anugerah Firdauzi, Masaya Miyahara
, Kenichi Okada
, Akira Matsuzawa:
Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector. IEICE Trans. Electron. 102-C(7): 520-529 (2019) - 2018
- [c3]Jian Sen Teh
, Liter Siek
, Abdel Martinez Alonso
, Anugerah Firdauzi, Akira Matsuzawa:
A 14-b, 850fs Fully Synthesizable Stochastic-Based Branching Time-to-Digital Converter in 65nm CMOS. ISCAS 2018: 1-5 - 2017
- [j1]Anugerah Firdauzi, Zule Xu, Masaya Miyahara
, Akira Matsuzawa:
High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator. IEICE Trans. Electron. 100-C(6): 548-559 (2017) - 2016
- [c2]Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada
, Akira Matsuzawa:
A 2 GHz 3.1 mW type-I digital ring-based PLL. ESSCIRC 2016: 205-208 - [c1]Anugerah Firdauzi, Zule Xu, Masaya Miyahara, Akira Matsuzawa:
A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC. ISCAS 2016: 57-60
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last updated on 2024-04-25 05:55 CEST by the dblp team
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