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2020 – today
- 2023
[j6]Fei Yuan
, Parth Parekh, Yushi Zhou:
Bi-Directional Gated Ring Oscillator Time Integrator. IEEE Trans. Circuits Syst. I Regul. Pap. 70(9): 3461-3473 (2023)- [i2]Parth Parekh, Cedric McGuire, Jake Imyak:
Underwater Robotics Semantic Parser Assistant. CoRR abs/2301.12134 (2023) - 2022
- [j5]Parth Parekh, Fei Yuan, Yushi Zhou:
Gated Vernier delay line time integrator with applications in ΔΣ time-to-digital converter. Microelectron. J. 119: 105316 (2022) - [j4]Parth Parekh, Fei Yuan, Yushi Zhou:
Improved Metastability of True Single-Phase Clock D-Flipflops With Applications in Vernier Time-to-Digital Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 1102-1114 (2022) - [c8]Parth Parekh, Fei Yuan, Yushi Zhou:
Bi-Directional Gated Ring Oscillator Time Integrator for Time-Based Mixed-Signal Processing. MWSCAS 2022: 1-4 - [c7]Parth Parekh, Fei Yuan, Yushi Zhou:
All-Digital Bi-Directional Gated Ring Oscillator Time Integrator for Mixed-Mode Signal Processing. NEWCAS 2022: 25-29 - 2021
- [c6]Parth Parekh, Fei Yuan, Yushi Zhou:
Gated Vernier Delay Line Time Integrator for Time-Mode Signal Processing. MWSCAS 2021: 1082-1085 - 2020
- [j3]Fei Yuan, Parth Parekh:
Time-based all-digital Δ Σ time-to-digital converter with pre-skewed bi-directional gated delay line time integrator. IET Circuits Devices Syst. 14(1): 25-34 (2020) - [j2]Fei Yuan, Parth Parekh:
Analysis and Design of an All-Digital ∆Σ TDC via Time-Mode Signal Processing. IEEE Trans. Circuits Syst. II Express Briefs 67-II(6): 994-998 (2020) - [c5]Parth Parekh, Fei Yuan, Yushi Zhou:
Area/Power-Efficient True-Single-Phase-Clock D-Flipflops with Improved Metastability. MWSCAS 2020: 182-185 - [c4]Parth Parekh, Fei Yuan, Yushi Zhou:
All-Digital Time Integrator Using Bi-Directional Gated Vernier Delay Line. MWSCAS 2020: 321-324
2010 – 2019
- 2019
- [c3]Fei Yuan, Parth Parekh:
Time-Mode All-Digital Delta-Sigma Time-to-Digital Converter with Process Uncertainty Calibration. MWSCAS 2019: 489-492 - [c2]Fei Yuan, Parth Parekh:
All-Digital ∆Σ TDC with Current-Starved Bi-Directional Gated Delay Line Time Integrator. MWSCAS 2019: 493-496 - 2018
- [j1]Young Jun Park, Parth Parekh, Fei Yuan:
All-digital ΔΣ time-to-digital converter with Bi-Directional gated delay line time integrator. Microelectron. J. 81: 179-191 (2018) - [c1]Parth Parekh, Fei Yuan:
Power-Silicon Efficient All-Digital △Σ TDC with Differential Gated Delay Line Time Integrator. NEWCAS 2018: 191-194 - 2016
- [i1]Edward Yu, Parth Parekh:
A Bayesian Ensemble for Unsupervised Anomaly Detection. CoRR abs/1610.07677 (2016)
Coauthor Index
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