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Jiu Xiong
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2020 – today
- 2022
- [j1]Jiu Xiong
, Jin Liu
, Hoi Lee
:
A Continuous-Time Sigma-Delta Modulator With Continuous-Time Delay-Based Integrator. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 914-918 (2022) - [c6]Jiu Xiong, Jeniffer Zhao, Jin Liu, Hoi Lee:
A 3rd Order CT-ΣΔ Modulator with a Hybrid Loop Filter Employing Passive and Continuous-Time Delay Based Integrators. ISCAS 2022: 1230-1233
2010 – 2019
- 2019
- [c5]Jiu Xiong, Jiajun Ren, Jin Liu:
An 8-b 2b/cycle Asynchronous SAR ADC with Capacitive Divider Based RC-DAC. MWSCAS 2019: 762-765 - [c4]Jiajun Ren, Jiu Xiong, Jin Liu:
ADC Quantization with Overlapping Metastability Zones and Dual Reference Calibration. MWSCAS 2019: 896-899 - 2018
- [c3]Jiajun Ren, Jiu Xiong, Jin Liu:
High-Speed ADC Quantization with Overlapping Metastability Zones. MWSCAS 2018: 234-237 - 2017
- [c2]Yucheng Dai, Yahia R. Ramadan, Hlaing Minn, Jiu Xiong, Jin Liu, Alan Gatherer:
A New Receiver Architecture for MIMO Beam-Forming Applications. GLOBECOM 2017: 1-6 - [c1]Jiu Xiong, Jin Liu, Yucheng Dai, Hlaing Minn:
An open-loop 28GHz 16-phase clock generator in 28nm CMOS. MWSCAS 2017: 305-308
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last updated on 2024-04-25 05:36 CEST by the dblp team
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