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2020 – today
- 2024
[c3]Feng-Min Lee, Po-Hao Tseng, Yu-Yu Lin, Yu-Hsuan Lin, Wei-Lun Weng, Nei-Chih Lin, Po-Jung Sung, Chien-Ting Wu, Chih-Chao Yang, Wen-Fa Wu, Chang-Hong Shen, Tuo-Hung Hou, Ming-Hsiu Lee, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu:
Bit-Cost-Scalable 3D DRAM Architecture and Unit Cell First Demonstrated with Integrated Gate-Around and Channel-Around IGZO FETs. VLSI Technology and Circuits 2024: 1-2- [c2]Bo-Jheng Shih, Yu-Ming Pan, Hao-Tung Chung, Chieh-Ling Lee, I-Chun Hsieh, Nein-Chih Lin, Chih-Chao Yang, Po-Tsang Huang, Hung-Ming Chen, Chiao-Yen Wang, Huan-Yu Chiu, Huang-Chung Cheng, Chang-Hong Shen, Wen-Fa Wu, Tuo-Hung Hou, Kuan-Neng Chen, Chenming Hu:
3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25×33mm2) Single-Crystalline Si on SiO2 by Elevated-Epi. VLSI Technology and Circuits 2024: 1-2
2010 – 2019
- 2018
- [j2]Chang-Fu Han, Yi-Zhe Guo, Chung-Jen Chung, Chang-Hong Shen, Jen-Fin Lin
:
Effects of SiO2 film thickness and operating temperature on thermally-induced failures in through-silicon-via structures. Microelectron. Reliab. 83: 1-13 (2018) - [j1]Hsin-Kai Fang, Kuei-Shu Chang-Liao, Chia-Hsin Cheng, Po-Yao Lin, Wen-Hsien Huang, Chang-Hong Shen, Jia-Min Shieh:
SiO2 tunneling and Si3N4/HfO2 trapping layers formed with low temperature processes on gate-all-around junctionless charge-trapping flash memory devices. Microelectron. Reliab. 91: 319-322 (2018) - [c1]Srivatsa Rangachar Srinivasa, Akshay Krishna Ramanathan, Xueqing Li, Wei-Hao Chen, Fu-Kuo Hsueh, Chih-Chao Yang, Chang-Hong Shen, Jia-Min Shieh, Sumeet Kumar Gupta, Meng-Fan Marvin Chang, Swaroop Ghosh, Jack Sampson, Vijaykrishnan Narayanan:
A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support. ISLPED 2018: 34:1-34:6
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