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ORCIDJaekwang Yun
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2020 – today
- 2024
[j7]Jaekwang Yun
, Sang-Yoon Lee, Jaewook Kim, Joo-Hyung Chae, Suhwan Kim, Yong-Un Jeong:
A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces. IEEE J. Solid State Circuits 59(9): 2971-2982 (2024)- [c6]Sanghyuk Seo, Yong-Un Jeong, Jaekwang Yun, Jaewook Kim, Suhwan Kim:
A 0.77-pJ/bit 40-Gb/s/pin Single-Ended Hybrid DAC-Based Transmitter for Memory Interfaces. ISCAS 2024: 1-5 - 2023
- [j6]Jaewook Kim, Jaekwang Yun, Joo-Hyung Chae, Suhwan Kim:
A 50-1600 MHz Wide-Range Digital Duty-Cycle Corrector With Counter-Based Half-Cycle Delay Line. IEEE Access 11: 30555-30561 (2023) - 2022
- [j5]Yong-Un Jeong, Sungphil Choi, Joo-Hyung Chae, Jaekwang Yun, Shin-Hyun Jeong, Suhwan Kim:
A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 1125-1134 (2022) - [j4]Sangyoon Lee, Yong-Un Jeong, Jaekwang Yun, Joo-Hyung Chae, Suhwan Kim:
A Low-Power DRAM Transmitter With Phase and Current-Mode Amplitude Equalization to Improve Impedance Matching. IEEE Trans. Circuits Syst. II Express Briefs 69(11): 4208-4212 (2022) - [c5]Sangyoon Lee, Jaekwang Yun, Suhwan Kim:
A 78.8fJ/b/mm 12.0Gb/s/Wire Capacitively Driven On-Chip Link Over 5.6mm with an FFE-Combined Ground-Forcing Biasing Technique for DRAM Global Bus Line in 65nm CMOS. ISSCC 2022: 454-456 - 2020
- [j3]Yong-Un Jeong, Jihwan Park, Mino Kim, Joo-Hyung Chae, Jaekwang Yun, Hyunjoong Lee, Suhwan Kim:
A 9Gb/s Wide Output Range Transmitter With 2D Binary-Segmented Driver and Dual-Loop Calibration for Intra-Panel Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1589-1593 (2020) - [j2]Sangyoon Lee, Han-Gon Ko, Joo-Hyung Chae, Soyeong Shin, Jaekwang Yun, Deog-Kyoon Jeong, Suhwan Kim:
A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1735-1739 (2020) - [j1]Soyeong Shin, Han-Gon Ko, Chan-Ho Kye, Sang-Yoon Lee, Jaekwang Yun, Doobock Lee, Hae-Kang Jung, Suhwan Kim, Deog-Kyoon Jeong:
A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1814-1818 (2020) - [c4]Jaekwang Yun, Sangyoon Lee, Yong-Un Jeong, Shin-Hyun Jeong, Suhwan Kim:
A 0.4-1.7GHz Wide Range Fractional-N PLL Using a Transition-Detection DAC for Jitter Reduction. A-SSCC 2020: 1-4
2010 – 2019
- 2019
- [c3]Yong-Un Jeong, Joo-Hyung Chae, Sungphil Choi, Jaekwang Yun, Shin-Hyun Jeong, Suhwan Kim:
A Low-Power and Low-Noise 20: 1 Serializer with Two Calibration Loops in 55-nm CMOS. ISLPED 2019: 1-6 - [c2]Han-Gon Ko, Soyeong Shin, Chan-Ho Kye, Sang-Yoon Lee, Jaekwang Yun, Hae-Kang Jung, Doobock Lee, Suhwan Kim, Deog-Kyoon Jeong:
A 370-fJ/b, 0.0056 mm2/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop. VLSI Circuits 2019: 94- - 2018
- [c1]Jae-Whan Lee, Joo-Hyung Chae, Jihwan Park, Hyunkyu Park, Jaekwang Yun, Suhwan Kim:
Energy-Efficient Dynamic Comparator with Active Inductor for Receiver of Memory Interfaces. ISLPED 2018: 10:1-10:6
Coauthor Index
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