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ORCIDMahendra Rathor
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2020 – today
- 2024
[j16]Mahendra Rathor
, Girraj Prasad Rathor:
Hard-Sign: A Hardware Watermarking Scheme Using Dated Handwritten Signature. IEEE Des. Test 41(2): 75-83 (2024)- [j15]Mahendra Rathor, Anirban Sengupta:
Revisiting Black-Hat HLS: A Lightweight Countermeasure to HLS-Aided Trojan Attack. IEEE Embed. Syst. Lett. 16(2): 170-173 (2024) - [j14]Mahendra Rathor, Aditya Anshul, Anirban Sengupta:
Securing Reusable IP Cores Using Voice Biometric Based Watermark. IEEE Trans. Dependable Secur. Comput. 21(4): 2735-2749 (2024) - [c7]Akash Panzade, Deepak Kumar, Mahendra Rathor, Urbi Chatterjee:
Vig-WaR: Vigilantly Watching Ransomware for Robust Trapping and Containment. VLSID 2024: 449-454 - 2023
- [j13]Mahendra Rathor, Aditya Anshul, K. Bharath, Rahul Chaurasia, Anirban Sengupta:
Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores. Comput. Electr. Eng. 105: 108476 (2023) - [j12]Anirban Sengupta, Mahendra Rathor, Rahul Chaurasia:
Biometrics for Hardware Security and Trust: Discussion and Analysis. IT Prof. 25(4): 36-44 (2023) - [j11]Mahendra Rathor, Anirban Sengupta, Rahul Chaurasia, Aditya Anshul:
Exploring Handwritten Signature Image Features for Hardware Security. IEEE Trans. Dependable Secur. Comput. 20(5): 3687-3698 (2023) - [c6]Mahendra Rathor, Vishesh Mishra, Urbi Chatterjee:
Aiding to Multimedia Accelerators: A Hardware Design for Efficient Rounding of Binary Floating Point Numbers. DATE 2023: 1-6 - 2022
- [c5]Abhishek Revskar, Mahendra Rathor, Urbi Chatterjee:
Dual-Tone Multi-Frequency Assisted Acoustic Side Channel Attack to Retrieve Dialled Call Log. SPACE 2022: 185-203 - [p1]Anirban Sengupta, Mahendra Rathor:
Hardware (IP) Watermarking During Behavioral Synthesis. Behavioral Synthesis for Hardware Security 2022: 119-145 - [i1]Chandan Kumar, Mahendra Rathor, Urbi Chatterjee:
Sorting Attacks Resilient Authentication Protocol for CMOS Image Sensor Based PUF. IACR Cryptol. ePrint Arch. 2022: 1402 (2022) - 2021
- [j10]Anirban Sengupta, Mahendra Rathor:
Facial Biometric for Securing Hardware Accelerators. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 112-123 (2021) - [c4]Mahendra Rathor, Anirban Sengupta:
Signature Biometric based Authentication of IP Cores for Secure Electronic Systems. iSES 2021: 384-388 - 2020
- [j9]Anirban Sengupta, Mahendra Rathor:
Structural Obfuscation and Crypto-Steganography-Based Secured JPEG Compression Hardware for Medical Imaging Systems. IEEE Access 8: 6543-6565 (2020) - [j8]Anirban Sengupta, Mahendra Rathor:
Enhanced Security of DSP Circuits Using Multi-Key Based Structural Obfuscation and Physical-Level Watermarking for Consumer Electronics Systems. IEEE Trans. Consumer Electron. 66(2): 163-172 (2020) - [j7]Mahendra Rathor, Anirban Sengupta:
IP Core Steganography Using Switch Based Key-Driven Hash-Chaining and Encoding for Securing DSP Kernels Used in CE Systems. IEEE Trans. Consumer Electron. 66(3): 251-260 (2020) - [j6]Anirban Sengupta, Mahendra Rathor:
Obfuscated Hardware Accelerators for Image Processing Filters - Application Specific and Functionally Reconfigurable Processors. IEEE Trans. Consumer Electron. 66(4): 386-395 (2020) - [j5]Anirban Sengupta, Mahendra Rathor:
Securing Hardware Accelerators for CE Systems Using Biometric Fingerprinting. IEEE Trans. Very Large Scale Integr. Syst. 28(9): 1979-1992 (2020) - [c3]Mahendra Rathor, Pallabi Sarkar, Vipul Kumar Mishra, Anirban Sengupta:
Securing IP Cores in CE Systems using Key-driven Hash-chaining based Steganography. ICCE-Berlin 2020: 1-4
2010 – 2019
- 2019
- [j4]Anirban Sengupta, Mahendra Rathor:
Security of Functionally Obfuscated DSP Core Against Removal Attack Using SHA-512 Based Key Encryption Hardware. IEEE Access 7: 4598-4610 (2019) - [j3]Mahendra Rathor, Anirban Sengupta:
Robust Logic locking for Securing Reusable DSP Cores. IEEE Access 7: 120052-120064 (2019) - [j2]Anirban Sengupta, Mahendra Rathor:
Protecting DSP Kernels Using Robust Hologram-Based Obfuscation. IEEE Trans. Consumer Electron. 65(1): 99-108 (2019) - [j1]Anirban Sengupta, Mahendra Rathor:
IP Core Steganography for Protecting DSP Kernels Used in CE Systems. IEEE Trans. Consumer Electron. 65(4): 506-515 (2019) - [c2]Mahendra Rathor, Anirban Sengupta:
Enhanced Functional Obfuscation of DSP core using Flip-Flops and Combinational logic. ICCE-Berlin 2019: 1-5 - [c1]Anirban Sengupta, Mahendra Rathor:
Improved Delay Estimation Model for Loop based DSP cores. ICCE 2019: 1-4
Coauthor Index
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last updated on 2024-10-07 21:23 CEST by the dblp team
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