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ORCIDJonghyuck Choi
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2020 – today
- 2024
[j22]Jonghyuck Choi
, Yoonjae Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim:
A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces. IEEE J. Solid State Circuits 59(4): 1261-1270 (2024)- [j21]Jincheol Sim, Changmin Sim, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Jong-Min Kim, Ju-Hyung Lee, Young-Chai Ko, Chulwoo Kim:
A 10-Gb/s Wireline Receiver Using Linear Baud-Rate CDR and Analog Equalizer for Free Space Optical Communication Over 10- and 100-m Distances. IEEE J. Solid State Circuits 59(6): 1835-1846 (2024) - [j20]Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Hwaseok Shin, Junseob So, Seonbeen Lee, Chulwoo Kim:
A Wireline Transceiver With 3-bit per Symbol Using Common-Mode NRZ and Differential-Mode PAM-4 Signaling Techniques. IEEE J. Solid State Circuits 59(8): 2518-2528 (2024) - [j19]Seongcheol Kim, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Changmin Sim, Junseob So, Taehyeong Park, Chulwoo Kim:
Single-Ended PAM-4 Transmitters With Data Bus Inversion and ZQ Calibration for High-Speed Memory Interfaces. IEEE J. Solid State Circuits 59(10): 3432-3443 (2024) - [j18]Hyoshin Kang, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim:
A 13-Gb/s Single-Ended NRZ Receiver With 1-Sample Per 2-UI Using Data Edge Sampling for Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 71(7): 3328-3332 (2024) - [j17]Seungwoo Park, Yoonjae Choi, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Changmin Sim, Seongcheol Kim, Chulwoo Kim:
A 0.45 pJ/b 24 Gb/s NRZ Receiver Data-Path Using Half-Baud-Rate Duobinary Sampling. IEEE Trans. Circuits Syst. II Express Briefs 71(9): 4096-4100 (2024) - 2023
- [j16]Yoonjae Choi, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Chulwoo Kim:
A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces. IEEE J. Solid State Circuits 58(7): 2005-2015 (2023) - [j15]Youngwook Kwon, Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Seungwoo Park, Kyeong-Min Kim, Changkyu Choi, Hae-Kang Jung, Chulwoo Kim:
A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces. IEEE J. Solid State Circuits 58(8): 2314-2325 (2023) - [j14]Jincheol Sim, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Chulwoo Kim:
PAM-4 Receiver With 1-Tap DFE Using Clocked Comparator Offset Instead of Threshold Voltages for Improved LSB BER Performance. IEEE Trans. Circuits Syst. I Regul. Pap. 70(5): 1907-1916 (2023) - [j13]Yoonjae Choi, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Changmin Sim, Chulwoo Kim:
A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector. IEEE Trans. Circuits Syst. I Regul. Pap. 70(7): 2734-2743 (2023) - [j12]Seongcheol Kim, Jincheol Sim, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Chulwoo Kim:
A 15-Gb/s Single-Ended NRZ Receiver Using Self-Referenced Technique With 1-Tap Latched DFE for DRAM Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 70(1): 101-105 (2023) - [j11]Jonghyuck Choi, Yoonjae Choi, Hyunsu Park, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Chulwoo Kim:
A 16-Gb/s NRZ Receiver With 0.0019-pJ/bit/dB 1-Tap Charge-Redistribution DFE. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 904-908 (2023) - [c4]Seungwoo Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Hyunsu Park, Youngwook Kwon, Chulwoo Kim:
A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications. ISSCC 2023: 118-119 - 2022
- [j10]Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Chulwoo Kim:
A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage Variations. IEEE J. Solid State Circuits 57(2): 562-572 (2022) - [j9]Jonghyuck Choi, Yoonjae Choi, Hyunsu Park, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Chulwoo Kim:
Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 69(8): 3416-3427 (2022) - [j8]Jincheol Sim, Yeonho Lee, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Chulwoo Kim:
A 25 Gb/s Wireline Receiver With Feedforward and Feedback Equalizers at Analog Front-End. IEEE Trans. Circuits Syst. II Express Briefs 69(2): 404-408 (2022) - [j7]Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Chulwoo Kim:
A 2.4-8 GHz Phase Rotator Delay-Locked Loop Using Cascading Structure for Direct Input-Output Phase Detection. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 794-798 (2022) - [j6]Youngwook Kwon, Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Seungwoo Park, Chulwoo Kim:
A 15 Gb/s Non-Return-to-Zero Transmitter With 1-Tap Pre-Emphasis Feed-Forward Equalizer for Low-Power Ground Terminated Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2737-2741 (2022) - [c3]Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Junyoung Song, Chulwoo Kim:
A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM Interfaces. ISSCC 2022: 1-3 - 2021
- [j5]Yoonjae Choi, Sewook Hwang, Yeonho Lee, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Chulwoo Kim:
A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector. IEEE Access 9: 118907-118918 (2021) - [j4]Hyunsu Park, Junyoung Song, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Jeongsik Yoo, Chulwoo Kim:
30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links. IEEE J. Solid State Circuits 56(2): 581-590 (2021) - [j3]Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Gyutae Park, Jinil Chung, Kyeong-Min Kim, Hae-Kang Jung, Hyungsoo Kim, Junhyun Chun, Chulwoo Kim:
A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line. IEEE J. Solid State Circuits 56(6): 1886-1896 (2021) - [j2]Yoonjae Choi, Yeonho Lee, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Chulwoo Kim:
A 0.99-pJ/b 15-Gb/s Counter-Based Adaptive Equalizer Using Single Comparator in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 68(10): 3189-3193 (2021) - 2020
- [j1]Dongkyun Kim, Kibong Koo, Yongmi Kim, Dong-Uk Lee, Jaejin Lee, Ki Hun Kwon, Byeongchan Choi, Hongjung Kim, Sanghyun Ku, Jong-Sam Kim, Seungwook Oh, Minsu Park, Dain Im, Yongsung Lee, Mingyu Park, Jonghyuck Choi, Junhyun Chun, Kyowon Jin, Sungchun Jang, Jun-Yong Song, Hankyu Chi, Geunho Choi, Sunmyung Choi, Changhyun Kim, Minsik Han:
A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx. IEEE J. Solid State Circuits 55(1): 167-177 (2020)
2010 – 2019
- 2019
- [c2]Dongkyun Kim, Minsu Park, Sungchun Jang, Jun-Yong Song, Hankyu Chi, Geunho Choi, Sunmyung Choi, Jaeil Kim, Changhyun Kim, Kyung Whan Kim, Kibong Koo, Seonghwi Song, Yongmi Kim, Dong-Uk Lee, Jaejin Lee, Dae Suk Kim, Ki Hun Kwon, Minsik Han, Byeongchan Choi, Hongjung Kim, Sanghyun Ku, Yeonuk Kim, Jong-Sam Kim, Sanghui Kim, Youngsuk Seo, Seungwook Oh, Dain Im, Haksong Kim, Jonghyuck Choi, Jinil Chung, Changhyun Lee, Yongsung Lee, Joo-Hwan Cho, Junhyun Chun, Jonghoon Oh:
A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme. ISSCC 2019: 380-382 - [c1]Hyunsu Park, Junyoung Song, Yeonho Lee, Jincheol Sim, Jonghyuck Choi, Chulwoo Kim:
A 3-bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver Using One-Tap DFE for Next-Generation Memory Interface. ISSCC 2019: 382-384
Coauthor Index
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