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Hyunsu Park
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2020 – today
- 2024
- [j18]Jincheol Sim
, Changmin Sim
, Hyunsu Park, Yoonjae Choi
, Jonghyuck Choi
, Youngwook Kwon, Seungwoo Park, Seongcheol Kim
, Jong-Min Kim, Ju-Hyung Lee
, Young-Chai Ko
, Chulwoo Kim
:
A 10-Gb/s Wireline Receiver Using Linear Baud-Rate CDR and Analog Equalizer for Free Space Optical Communication Over 10- and 100-m Distances. IEEE J. Solid State Circuits 59(6): 1835-1846 (2024) - [c9]Jaehyeok Yang, Hyeongjun Ko, Kyunghoon Kim, Hyunsu Park, Jihwan Park, Ji-Hyo Kang, Jin-Youp Cha, Seongjin Kim, Youngtaek Kim, Minsoo Park, Gangsik Lee, Keonho Lee, Sanghoon Lee, Gyunam Jeon, Sera Jeong, Yongsuk Joo, Jaehoon Cha, Seonwoo Hwang, Boram Kim, Sang-Yeon Byeon, Sungkwon Lee, Hyeonyeol Park, Joohwan Cho, Jonghwan Kim:
13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry. ISSCC 2024: 232-234 - 2023
- [j17]Yoonjae Choi
, Hyunsu Park, Jonghyuck Choi
, Jincheol Sim
, Youngwook Kwon, Seungwoo Park, Seongcheol Kim
, Changmin Sim
, Chulwoo Kim
:
A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces. IEEE J. Solid State Circuits 58(7): 2005-2015 (2023) - [j16]Youngwook Kwon, Hyunsu Park, Yoonjae Choi
, Jincheol Sim
, Jonghyuck Choi
, Seungwoo Park, Kyeong-Min Kim, Changkyu Choi, Hae-Kang Jung, Chulwoo Kim
:
A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces. IEEE J. Solid State Circuits 58(8): 2314-2325 (2023) - [j15]Jincheol Sim
, Hyunsu Park, Yoonjae Choi
, Jonghyuck Choi
, Youngwook Kwon, Chulwoo Kim
:
PAM-4 Receiver With 1-Tap DFE Using Clocked Comparator Offset Instead of Threshold Voltages for Improved LSB BER Performance. IEEE Trans. Circuits Syst. I Regul. Pap. 70(5): 1907-1916 (2023) - [j14]Yoonjae Choi
, Hyunsu Park, Jonghyuck Choi
, Jincheol Sim
, Youngwook Kwon, Seungwoo Park, Changmin Sim
, Chulwoo Kim
:
A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector. IEEE Trans. Circuits Syst. I Regul. Pap. 70(7): 2734-2743 (2023) - [j13]Seongcheol Kim
, Jincheol Sim
, Hyunsu Park, Yoonjae Choi
, Jonghyuck Choi
, Chulwoo Kim
:
A 15-Gb/s Single-Ended NRZ Receiver Using Self-Referenced Technique With 1-Tap Latched DFE for DRAM Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 70(1): 101-105 (2023) - [j12]Jonghyuck Choi
, Yoonjae Choi
, Hyunsu Park, Jincheol Sim
, Youngwook Kwon, Seungwoo Park, Seongcheol Kim
, Chulwoo Kim
:
A 16-Gb/s NRZ Receiver With 0.0019-pJ/bit/dB 1-Tap Charge-Redistribution DFE. IEEE Trans. Circuits Syst. II Express Briefs 70(3): 904-908 (2023) - [c8]Seungwoo Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Hyunsu Park, Youngwook Kwon, Chulwoo Kim:
A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications. ISSCC 2023: 118-119 - 2022
- [j11]Hyunsu Park, Jincheol Sim, Yoonjae Choi
, Jonghyuck Choi
, Youngwook Kwon, Chulwoo Kim
:
A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage Variations. IEEE J. Solid State Circuits 57(2): 562-572 (2022) - [j10]Jonghyuck Choi
, Yoonjae Choi
, Hyunsu Park, Jincheol Sim
, Youngwook Kwon, Seungwoo Park, Chulwoo Kim
:
Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 69(8): 3416-3427 (2022) - [j9]Jincheol Sim, Yeonho Lee
, Hyunsu Park, Yoonjae Choi
, Jonghyuck Choi
, Chulwoo Kim
:
A 25 Gb/s Wireline Receiver With Feedforward and Feedback Equalizers at Analog Front-End. IEEE Trans. Circuits Syst. II Express Briefs 69(2): 404-408 (2022) - [j8]Hyunsu Park, Jincheol Sim, Yoonjae Choi
, Jonghyuck Choi
, Youngwook Kwon, Chulwoo Kim
:
A 2.4-8 GHz Phase Rotator Delay-Locked Loop Using Cascading Structure for Direct Input-Output Phase Detection. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 794-798 (2022) - [j7]Youngwook Kwon, Hyunsu Park, Yoonjae Choi
, Jincheol Sim
, Jonghyuck Choi
, Seungwoo Park, Chulwoo Kim
:
A 15 Gb/s Non-Return-to-Zero Transmitter With 1-Tap Pre-Emphasis Feed-Forward Equalizer for Low-Power Ground Terminated Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2737-2741 (2022) - [c7]Jong-Min Kim
, Ju-Hyung Lee, Yeongrok Lee, Hong-Seol Cha, Hyunsu Park, Jincheol Sim, Chulwoo Kim, Young-Chai Ko:
Experimental Demonstration of RoFSO Transmission Combining WLAN Standard and WDM-FSO over 100m Distance. INFOCOM Workshops 2022: 1-2 - [c6]Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Junyoung Song, Chulwoo Kim:
A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM Interfaces. ISSCC 2022: 1-3 - 2021
- [j6]Yoonjae Choi
, Sewook Hwang, Yeonho Lee
, Hyunsu Park, Jonghyuck Choi
, Jincheol Sim, Chulwoo Kim
:
A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector. IEEE Access 9: 118907-118918 (2021) - [j5]Hyunsu Park, Junyoung Song
, Jincheol Sim, Yoonjae Choi
, Jonghyuck Choi
, Jeongsik Yoo, Chulwoo Kim
:
30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links. IEEE J. Solid State Circuits 56(2): 581-590 (2021) - [j4]Hyunsu Park, Jincheol Sim, Yoonjae Choi
, Jonghyuck Choi
, Youngwook Kwon, Seungwoo Park, Gyutae Park, Jinil Chung, Kyeong-Min Kim, Hae-Kang Jung, Hyungsoo Kim, Junhyun Chun, Chulwoo Kim
:
A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line. IEEE J. Solid State Circuits 56(6): 1886-1896 (2021) - [j3]Yoonjae Choi
, Yeonho Lee
, Hyunsu Park, Jonghyuck Choi
, Jincheol Sim, Youngwook Kwon, Chulwoo Kim
:
A 0.99-pJ/b 15-Gb/s Counter-Based Adaptive Equalizer Using Single Comparator in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 68(10): 3189-3193 (2021) - [c5]Jincheol Sim, Hyunsu Park, Youngwook Kwon, Seongcheol Kim, Chulwoo Kim:
A 1-3.2 GHz 0.6 mW/GHz Duty-Cycle-Corrector Using Bangbang Duty-Cyle-Detector. ISCAS 2021: 1-4 - 2020
- [j2]Youngbog Yoon, Hyunsu Park, Chulwoo Kim
:
A DLL-Based Quadrature Clock Generator With a 3-Stage Quad Delay Unit Using the Sub-Range Phase Interpolator for Low-Jitter and High-Phase Accuracy DRAM Applications. IEEE Trans. Circuits Syst. 67-II(11): 2342-2346 (2020) - [c4]Hyunsu Park, Amanda Ruth Maple, Hyowon Lee:
Effects of Fractal Electrode Geometry in Charge Injection Capacity of TiN Microelectrodes. EMBC 2020: 3371-3374
2010 – 2019
- 2019
- [c3]Hyunsu Park, Junyoung Song, Yeonho Lee, Jincheol Sim, Jonghyuck Choi, Chulwoo Kim:
A 3-bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver Using One-Tap DFE for Next-Generation Memory Interface. ISSCC 2019: 382-384 - 2018
- [j1]Jeongsik Yoo, Yeonho Lee, Yoonjae Choi
, Hyunsu Park, Sanghune Park, Chulwoo Kim
:
A Low-Power Post-LPDDR4 Interface Using AC Termination at RX and an Active Inductor at TX. IEEE Trans. Circuits Syst. II Express Briefs 65-II(6): 789-793 (2018) - [c2]Tran Nguyen, Stephanie Lam, Hyunsu Park, Riyi Shi, Hyowon Lee:
Development of Flexible Glutamate Biosensor Using Activated Carbon - Pt Microparticle Composite Ink. IEEE SENSORS 2018: 1-4 - 2016
- [c1]Hyunsu Park, Simon John, Hyowon Lee
:
Low-cost rapid prototyping of liquid crystal polymer based magnetic microactuators for glaucoma drainage devices. EMBC 2016: 4212-4215
Coauthor Index
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last updated on 2024-06-19 20:56 CEST by the dblp team
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