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2020 – today
- 2023
[j5]Vikram Jain
, Juan Sebastian Piedrahita Giraldo, Jaro De Roose, Linyan Mei, Bert Boons, Marian Verhelst:
TinyVers: A Tiny Versatile System-on-Chip With State-Retentive eMRAM for ML Inference at the Extreme Edge. IEEE J. Solid State Circuits 58(8): 2360-2371 (2023)- [c11]Victor J. B. Jung, Arne Symons, Linyan Mei, Marian Verhelst, Luca Benini:
SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators. AICAS 2023: 1-5 - [c10]Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Friedemann Zenke, Frank K. Gürkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, Sam Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu, Henk Corporaal:
PetaOps/W edge-AI $\mu$ Processors: Myth or reality? DATE 2023: 1-6 - [c9]Linyan Mei, Koen Goetschalckx, Arne Symons, Marian Verhelst:
DeFiNES: Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators through Analytical Modeling. HPCA 2023: 570-583 - [c8]Jun Yin, Linyan Mei, Andre Guntoro, Marian Verhelst:
ACCO: Automated Causal CNN Scheduling Optimizer for Real-Time Edge Accelerators. ICCD 2023: 391-398 - [c7]Arne Symons, Linyan Mei, Steven Colleman, Pouya Houshmand, Sebastian Karl, Marian Verhelst:
Stream: A Modeling Framework for Fine-grained Layer Fusion on Multi-core DNN Accelerators. ISPASS 2023: 355-357 - [i7]Vikram Jain, Juan Sebastian Piedrahita Giraldo, Jaro De Roose, Linyan Mei, Bert Boons, Marian Verhelst:
TinyVers: A Tiny Versatile System-on-chip with State-Retentive eMRAM for ML Inference at the Extreme Edge. CoRR abs/2301.03537 (2023) - [i6]Victor J. B. Jung, Arne Symons, Linyan Mei, Marian Verhelst, Luca Benini:
SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators. CoRR abs/2304.12931 (2023) - 2022
- [j4]Ehab M. Ibrahim, Linyan Mei, Marian Verhelst:
Taxonomy and Benchmarking of Precision-Scalable MAC Arrays Under Enhanced DNN Dataflow Representation. IEEE Trans. Circuits Syst. I Regul. Pap. 69(5): 2013-2024 (2022) - [c6]Linyan Mei, Huichu Liu, Tony F. Wu, Huseyin Ekin Sumbul, Marian Verhelst, Edith Beigné:
A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows. DATE 2022: 220-225 - [c5]Vikram Jain, Juan Sebastian Piedrahita Giraldo, Jaro De Roose, Bert Boons, Linyan Mei, Marian Verhelst:
TinyVers: A 0.8-17 TOPS/W, 1.7 μW-20 mW, Tiny Versatile System-on-chip with State-Retentive eMRAM for Machine Learning Inference at the Extreme Edge. VLSI Technology and Circuits 2022: 20-21 - [d1]Linyan Mei, Koen Goetschalckx, Arne Symons, Marian Verhelst:
DeFiNES: A DSE Framework Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators. Zenodo, 2022
- [i5]Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Frank K. Zenke, Frank K. Gürkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, S. Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu, Henk Corporaal:
CONVOLVE: Smart and seamless design of smart edge processors. CoRR abs/2212.00873 (2022) - [i4]Linyan Mei, Koen Goetschalckx, Arne Symons, Marian Verhelst:
DeFiNES: Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators through Analytical Modeling. CoRR abs/2212.05344 (2022) - [i3]Arne Symons, Linyan Mei, Steven Colleman, Pouya Houshmand, Sebastian Karl, Marian Verhelst:
Towards Heterogeneous Multi-core Accelerators Exploiting Fine-grained Scheduling of Layer-Fused Deep Neural Networks. CoRR abs/2212.10612 (2022) - 2021
- [j3]Man Shi, Pouya Houshmand, Linyan Mei, Marian Verhelst:
Hardware-Efficient Residual Neural Network Execution in Line-Buffer Depth-First Processing. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(4): 690-700 (2021) - [j2]Linyan Mei, Pouya Houshmand, Vikram Jain, Juan Sebastian Piedrahita Giraldo, Marian Verhelst:
ZigZag: Enlarging Joint Architecture-Mapping Design Space Exploration for DNN Accelerators. IEEE Trans. Computers 70(8): 1160-1174 (2021) - [c4]Vikram Jain, Linyan Mei, Marian Verhelst:
Analyzing the Energy-Latency-Area-Accuracy Trade-off Across Contemporary Neural Networks. AICAS 2021: 1-4 - [c3]Arne Symons, Linyan Mei, Marian Verhelst:
LOMA: Fast Auto-Scheduling on DNN Accelerators through Loop-Order-based Memory Allocation. AICAS 2021: 1-4 - [c2]Steven Colleman, Thomas Verelst, Linyan Mei, Tinne Tuytelaars, Marian Verhelst:
Processor Architecture Optimization for Spatially Dynamic Neural Networks. VLSI-SoC 2021: 1-6 - [i2]Ehab M. Ibrahim, Linyan Mei, Marian Verhelst:
Survey and Benchmarking of Precision-Scalable MAC Arrays for Embedded DNN Processing. CoRR abs/2108.04773 (2021) - 2020
- [i1]Linyan Mei, Pouya Houshmand, Vikram Jain, Juan Sebastian Piedrahita Giraldo, Marian Verhelst:
ZigZag: A Memory-Centric Rapid DNN Accelerator Design Space Exploration Framework. CoRR abs/2007.11360 (2020)
2010 – 2019
- 2019
- [j1]Vincent Camus, Linyan Mei, Christian C. Enz, Marian Verhelst:
Review and Benchmarking of Precision-Scalable Multiply-Accumulate Unit Architectures for Embedded Neural-Network Processing. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(4): 697-711 (2019) - [c1]Linyan Mei, Mohit Dandekar, Dimitrios Rodopoulos, Jeremy Constantin, Peter Debacker, Rudy Lauwereins, Marian Verhelst:
Sub-Word Parallel Precision-Scalable MAC Engines for Efficient Embedded DNN Inference. AICAS 2019: 6-10
Coauthor Index
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