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2020 – today
- 2024
[j66]Nitish Satya Murthy
, Francky Catthoor, Marian Verhelst:
Optimization of block-scaled integer GeMMs for efficient DNN deployment on scalable in-order vector processors. J. Syst. Archit. 154: 103236 (2024)- [c137]Brian Plancher, Sebastian Büttrich, Jeremy Ellis, Neena Goveas, Laila D. Kazimierski, Jesús Alfonso López Sotelo, Milan Lukic, Diego Mendez, Rosdiadee Nordin, Andrés Oliva Trevisan, Massimo Pavan, Manuel Roveri, Marcus Rüb, Jackline Tum, Marian Verhelst, Salah Abdeljabar, Segun Adebayo, Thomas Amberg, Halleluyah Aworinde, José Bagur, Gregg Barrett, Nabil Benamar, Bharat S. Chaudhari, Ronald Criollo, David Cuartielles, José A. Ferreira Filho, Solomon Gizaw, Evgeni Gousev, Alessandro Grande, Shawn Hymel, Peter Ing, Prashant Manandhar, Pietro Manzoni, Boris Murmann, Eric Pan, Rytis Paskauskas, Ermanno Pietrosemoli, Tales C. Pimenta, Marcelo Rovai, Marco Zennaro, Vijay Janapa Reddi:
TinyML4D: Scaling Embedded Machine Learning Education in the Developing World. AAAI Spring Symposia 2024: 508-515 - [c136]Jonas Crols, Guilherme Paim, Shirui Zhao, Marian Verhelst:
TreeGRNG: Binary Tree Gaussian Random Number Generator for Efficient Probabilistic AI Hardware. DATE 2024: 1-6 - [c135]Man Shi, Vikram Jain, Antony Joseph, Maurice Meijer, Marian Verhelst:
BitWave: Exploiting Column-Based Bit-Level Sparsity for Deep Learning Acceleration. HPCA 2024: 732-746 - [c134]Joren Dumoulin, Pouya Houshmand, Vikram Jain, Marian Verhelst:
Enabling Efficient Hardware Acceleration of Hybrid Vision Transformer (ViT) Networks at the Edge. ISCAS 2024: 1-5 - [c133]Steven Colleman, Arne Symons, Victor J. B. Jung, Marian Verhelst:
Optimizing Layer-Fused Scheduling of Transformer Networks on Multi-accelerator Platforms. ISQED 2024: 1-6 - [c132]Pouya Houshmand, Jean-Sebastien Staelens, Ward van der Tempel, Marian Verhelst:
High-Rate. Compact In-Sensor Denoising for Active Stereo Vision Towards Embedded Depth Sensing. NewCAS 2024: 11-15 - [c131]Robin Geens, Man Shi, Arne Symons, Chao Fang, Marian Verhelst:
Energy Cost Modelling for Optimizing Large Language Model Inference on Hardware Accelerators. SOCC 2024: 1-6 - [c130]Nitish Satya Murthy, Nathan Laubeuf, Debjyoti Bhattacharjee, Francky Catthoor, Marian Verhelst:
Adaptive Block-Scaled GeMMs on Vector Processors for DNN Training at the Edge. VLSI-SoC 2024: 1-6 - [i35]Jiacong Sun, Pouya Houshmand, Marian Verhelst:
Analog or Digital In-memory Computing? Benchmarking through Quantitative Modeling. CoRR abs/2405.14978 (2024) - [i34]Josse Van Delm, Maarten Vandersteegen, Alessio Burrello, Giuseppe Maria Sarda, Francesco Conti, Daniele Jahier Pagliari, Luca Benini, Marian Verhelst:
HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms. CoRR abs/2406.07453 (2024) - [i33]Steven Colleman, Arne Symons, Victor J. B. Jung, Marian Verhelst:
Optimizing Layer-Fused Scheduling of Transformer Networks on Multi-accelerator Platforms. CoRR abs/2406.09804 (2024) - [i32]Steven Colleman, Man Shi, Marian Verhelst:
COAC: Cross-layer Optimization of Accelerator Configurability for Efficient CNN Processing. CoRR abs/2406.13752 (2024) - [i31]Man Shi, Steven Colleman, Charlotte VanDeMieroop, Antony Joseph, Maurice Meijer, Wim Dehaene, Marian Verhelst:
CMDS: Cross-layer Dataflow Optimization for DNN Accelerators Exploiting Multi-bank Memories. CoRR abs/2406.14574 (2024) - [i30]Giuseppe Maria Sarda, Nimish Shah, Debjyoti Bhattacharjee, Peter Debacker, Marian Verhelst:
Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis. CoRR abs/2407.11999 (2024) - [i29]Pouya Houshmand, Marian Verhelst:
Pack my weights and run! Minimizing overheads for in-memory computing accelerators. CoRR abs/2409.11437 (2024) - [i28]Mohamed Amine Hamdi, Francesco Daghero, Giuseppe Maria Sarda, Josse Van Delm, Arne Symons, Luca Benini, Marian Verhelst, Daniele Jahier Pagliari, Alessio Burrello:
MATCH: Model-Aware TVM-based Compilation for Heterogeneous Edge Devices. CoRR abs/2410.08855 (2024) - 2023
- [j65]Pouya Houshmand, Giuseppe Maria Sarda, Vikram Jain, Kodai Ueyoshi, Ioannis A. Papistas, Man Shi, Qilin Zheng, Debjyoti Bhattacharjee, Arindam Mallik, Peter Debacker, Diederik Verkest, Marian Verhelst:
DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge. IEEE J. Solid State Circuits 58(1): 203-215 (2023) - [j64]Koen Goetschalckx, Fengfeng Wu, Marian Verhelst:
DepFiN: A 12-nm Depth-First, High-Resolution CNN Processor for IO-Efficient Inference. IEEE J. Solid State Circuits 58(5): 1425-1435 (2023) - [j63]Vikram Jain, Juan Sebastian Piedrahita Giraldo, Jaro De Roose, Linyan Mei, Bert Boons, Marian Verhelst:
TinyVers: A Tiny Versatile System-on-Chip With State-Retentive eMRAM for ML Inference at the Extreme Edge. IEEE J. Solid State Circuits 58(8): 2360-2371 (2023) - [j62]Yingping Chen, Bernardo Tacca, Yunzhu Chen, Dwaipayan Biswas, Georges G. E. Gielen, Francky Catthoor, Marian Verhelst, Carolina Mora Lopez:
An Online-Spike-Sorting IC Using Unsupervised Geometry-Aware OSort Clustering for Efficient Embedded Neural-Signal Processing. IEEE J. Solid State Circuits 58(11): 2990-3002 (2023) - [j61]Thomas Bos, Marian Verhelst, Wim Dehaene:
An End-to-End Dual ASIC OFDM Transceiver for Ultrasound In-Body Communication. IEEE Trans. Biomed. Circuits Syst. 17(4): 664-673 (2023) - [j60]Peishuo Li, Tom R. Molderez, David H. Villamor, Antonin Prévoteau, Marian Verhelst:
A 96-Channel 40nm CMOS Potentiostat for Parallel Experiments on Microbial Electrochemical Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 70(1): 114-127 (2023) - [j59]Jun Yin, Marian Verhelst:
CNN-based Robust Sound Source Localization with SRP-PHAT for the Extreme Edge. ACM Trans. Embed. Comput. Syst. 22(3): 55:1-55:27 (2023) - [j58]Steven Colleman, Man Shi, Marian Verhelst:
COAC: Cross-Layer Optimization of Accelerator Configurability for Efficient CNN Processing. IEEE Trans. Very Large Scale Integr. Syst. 31(7): 945-958 (2023) - [c129]Victor J. B. Jung, Arne Symons, Linyan Mei, Marian Verhelst, Luca Benini:
SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators. AICAS 2023: 1-5 - [c128]Lotte Hendrickx, Arne Symons, Wiebe Van Ranst, Marian Verhelst, Toon Goedemé:
Hardware-aware NAS by Genetic Optimisation with a Design Space Exploration Simulator. CVPR Workshops 2023: 2275-2283 - [c127]Josse Van Delm, Maarten Vandersteegen, Alessio Burrello, Giuseppe Maria Sarda, Francesco Conti, Daniele Jahier Pagliari, Luca Benini, Marian Verhelst:
HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms. DAC 2023: 1-6 - [c126]Vikram Jain, Matheus A. Cavalcante, Nazareno Bruschi, Michael Rogenmoser, Thomas Benz, Andreas Kurth, Davide Rossi, Luca Benini, Marian Verhelst:
PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge. DAC 2023: 1-6 - [c125]Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Friedemann Zenke, Frank K. Gürkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, Sam Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu, Henk Corporaal:
PetaOps/W edge-AI $\mu$ Processors: Myth or reality? DATE 2023: 1-6 - [c124]Sebastian Karl, Arne Symons, Nael Fasfous, Marian Verhelst:
Genetic Algorithm-based Framework for Layer-Fused Scheduling of Multiple DNNs on Multi-core Systems. DATE 2023: 1-6 - [c123]Jun Yin, Stefano Damiano, Marian Verhelst, Toon van Waterschoot, Andre Guntoro:
Real-Time Acoustic Perception for Automotive Applications. DATE 2023: 1-6 - [c122]Weijie Jiang, Pouya Houshmand, Marian Verhelst, Wim Dehaene:
A 16nm 128kB high-density fully digital In Memory Compute macro with reverse SRAM pre-charge achieving 0.36TOPs/mm2, 256kB/mm2 and 23. 8TOPs/W. ESSCIRC 2023: 409-412 - [c121]Linyan Mei, Koen Goetschalckx, Arne Symons, Marian Verhelst:
DeFiNES: Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators through Analytical Modeling. HPCA 2023: 570-583 - [c120]Jiacong Sun, Pouya Houshmand, Marian Verhelst:
Analog or Digital In-Memory Computing? Benchmarking Through Quantitative Modeling. ICCAD 2023: 1-9 - [c119]Jun Yin, Linyan Mei, Andre Guntoro, Marian Verhelst:
ACCO: Automated Causal CNN Scheduling Optimizer for Real-Time Edge Accelerators. ICCD 2023: 391-398 - [c118]Giuseppe Maria Sarda, Nimish Shah, Debjyoti Bhattacharjee, Peter Debacker, Marian Verhelst:
Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis. IISWC 2023: 226-228 - [c117]Matteo Risso, Alessio Burrello, Giuseppe Maria Sarda, Luca Benini, Enrico Macii, Massimo Poncino, Marian Verhelst, Daniele Jahier Pagliari:
Precision-aware Latency and Energy Balancing on Multi-Accelerator Platforms for DNN Inference. ISLPED 2023: 1-6 - [c116]Arne Symons, Linyan Mei, Steven Colleman, Pouya Houshmand, Sebastian Karl, Marian Verhelst:
Stream: A Modeling Framework for Fine-grained Layer Fusion on Multi-core DNN Accelerators. ISPASS 2023: 355-357 - [c115]Man Shi, Steven Colleman, Charlotte VanDeMieroop, Antony Joseph, Maurice Meijer, Wim Dehaene, Marian Verhelst:
CMDS: Cross-layer Dataflow Optimization for DNN Accelerators Exploiting Multi-bank Memories. ISQED 2023: 1-8 - [c114]Yingping Chen, Bernardo Tacca, Yunzhu Chen, Dwaipayan Biswas, Georges G. E. Gielen, Francky Catthoor, Marian Verhelst, Carolina Mora Lopez:
A 384-Channel Online-Spike-Sorting IC Using Unsupervised Geo-OSort Clustering and Achieving 0.0013mm2/Ch and $1.78\mu \text{W/ch}$. ISSCC 2023: 486-487 - [i27]Vikram Jain, Juan Sebastian Piedrahita Giraldo, Jaro De Roose, Linyan Mei, Bert Boons, Marian Verhelst:
TinyVers: A Tiny Versatile System-on-chip with State-Retentive eMRAM for ML Inference at the Extreme Edge. CoRR abs/2301.03537 (2023) - [i26]Jason Yik, Soikat Hasan Ahmed, Zergham Ahmed, Brian Anderson, Andreas G. Andreou, Chiara Bartolozzi, Arindam Basu, Douwe den Blanken, Petrut Bogdan, Sander M. Bohté, Younes Bouhadjar, Sonia M. Buckley, Gert Cauwenberghs, Federico Corradi, Guido de Croon, Andreea Danielescu, Anurag Reddy Daram, Mike Davies, Yigit Demirag, Jason Eshraghian, Jeremy Forest, Steve B. Furber, Michael Furlong, Aditya Gilra, Giacomo Indiveri, Siddharth Joshi, Vedant Karia, Lyes Khacef, James C. Knight, Laura Kriener, Rajkumar Kubendran, Dhireesha Kudithipudi, Gregor Lenz, Rajit Manohar, Christian Mayr, Konstantinos P. Michmizos, Dylan R. Muir, Emre Neftci, Thomas Nowotny, Fabrizio Ottati, Ayça Özcelikkale, Noah Pacik-Nelson, Priyadarshini Panda, Pao-Sheng Sun, Melika Payvand, Christian Pehle, Mihai A. Petrovici, Christoph Posch, Alpha Renner, Yulia Sandamirskaya, Clemens JS Schaefer, André van Schaik, Johannes Schemmel, Catherine D. Schuman, Jae-sun Seo, Sumit Bam Shrestha, Manolis Sifalakis, Amos Sironi, Kenneth Michael Stewart, Terrence C. Stewart, Philipp Stratmann, Guangzhi Tang, Jonathan Timcheck, Marian Verhelst, Craig M. Vineyard, Bernhard Vogginger, Amirreza Yousefzadeh, Biyan Zhou, Fatima Tuz Zohora, Charlotte Frenkel, Vijay Janapa Reddi:
NeuroBench: Advancing Neuromorphic Computing through Collaborative, Fair and Representative Benchmarking. CoRR abs/2304.04640 (2023) - [i25]Victor J. B. Jung, Arne Symons, Linyan Mei, Marian Verhelst, Luca Benini:
SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators. CoRR abs/2304.12931 (2023) - [i24]Pouya Houshmand, Jiacong Sun, Marian Verhelst:
Benchmarking and modeling of analog and digital SRAM in-memory computing architectures. CoRR abs/2305.18335 (2023) - [i23]Matteo Risso, Alessio Burrello, Giuseppe Maria Sarda, Luca Benini, Enrico Macii, Massimo Poncino, Marian Verhelst, Daniele Jahier Pagliari:
Precision-aware Latency and Energy Balancing on Multi-Accelerator Platforms for DNN Inference. CoRR abs/2306.05060 (2023) - [i22]Vikram Jain, Matheus A. Cavalcante, Nazareno Bruschi, Michael Rogenmoser, Thomas Benz, Andreas Kurth, Davide Rossi, Luca Benini, Marian Verhelst:
PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge. CoRR abs/2308.00154 (2023) - 2022
- [j57]Geoffrey W. Burr, Sukhwan Lim, Boris Murmann, Rangharajan Venkatesan, Marian Verhelst:
Fair and Comprehensive Benchmarking of Machine Learning Processing Chips. IEEE Des. Test 39(3): 18-27 (2022) - [j56]Vikram Jain, Ninad Jadhav, Marian Verhelst:
Enabling real-time object detection on low cost FPGAs. J. Real Time Image Process. 19(1): 217-229 (2022) - [j55]Nimish Shah, Laura Isabel Galindez Olascoaga, Shirui Zhao, Wannes Meert, Marian Verhelst:
DPU: DAG Processing Unit for Irregular Graphs With Precision-Scalable Posit Arithmetic in 28 nm. IEEE J. Solid State Circuits 57(8): 2586-2596 (2022) - [j54]Ehab M. Ibrahim, Linyan Mei, Marian Verhelst:
Taxonomy and Benchmarking of Precision-Scalable MAC Arrays Under Enhanced DNN Dataflow Representation. IEEE Trans. Circuits Syst. I Regul. Pap. 69(5): 2013-2024 (2022) - [j53]Nimish Shah, Wannes Meert, Marian Verhelst:
GraphOpt: Constrained-Optimization-Based Parallelization of Irregular Graphs. IEEE Trans. Parallel Distributed Syst. 33(12): 3321-3332 (2022) - [c113]Steven Colleman, Peter Zhu, Wei Sun, Marian Verhelst:
Optimizing Accelerator Configurability for Mobile Transformer Networks. AICAS 2022: 142-145 - [c112]Thomas Bos, Marian Verhelst, Wim Dehaene:
A Flexible End-to-End Dual ASIC Transceiver for OFDM Ultrasound In-Body Communication. BioCAS 2022: 21-25 - [c111]Linyan Mei, Huichu Liu, Tony F. Wu, Huseyin Ekin Sumbul, Marian Verhelst, Edith Beigné:
A Uniform Latency Model for DNN Accelerators with Diverse Architectures and Dataflows. DATE 2022: 220-225 - [c110]Shirui Zhao, Nimish Shah, Wannes Meert, Marian Verhelst:
Discrete Samplers for Approximate Inference in Probabilistic Machine Learning. DATE 2022: 1221-1226 - [c109]Nitish Satya Murthy, Peter Vrancx, Nathan Laubeuf, Peter Debacker, Francky Catthoor, Marian Verhelst:
Learn to Learn on Chip: Hardware-aware Meta-learning for Quantized Few-shot Learning at the Edge. SEC 2022: 14-25 - [c108]Kodai Ueyoshi, Ioannis A. Papistas, Pouya Houshmand, Giuseppe Maria Sarda, Vikram Jain, Man Shi, Qilin Zheng, Juan Sebastian Piedrahita Giraldo, Peter Vrancx, Jonas Doevenspeck, Debjyoti Bhattacharjee, Stefan Cosemans, Arindam Mallik, Peter Debacker, Diederik Verkest, Marian Verhelst:
DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC. ISSCC 2022: 1-3 - [c107]Nimish Shah, Wannes Meert, Marian Verhelst:
DPU-v2: Energy-efficient execution of irregular directed acyclic graphs. MICRO 2022: 1288-1307 - [c106]Vikram Jain, Juan Sebastian Piedrahita Giraldo, Jaro De Roose, Bert Boons, Linyan Mei, Marian Verhelst:
TinyVers: A 0.8-17 TOPS/W, 1.7 μW-20 mW, Tiny Versatile System-on-chip with State-Retentive eMRAM for Machine Learning Inference at the Extreme Edge. VLSI Technology and Circuits 2022: 20-21 - [d1]Linyan Mei, Koen Goetschalckx, Arne Symons, Marian Verhelst:
DeFiNES: A DSE Framework Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators. Zenodo, 2022
- [i21]Zuzana Jelcicová, Marian Verhelst:
Delta Keyword Transformer: Bringing Transformers to the Edge through Dynamically Pruned Multi-Head Self-Attention. CoRR abs/2204.03479 (2022) - [i20]Maxim Bonnaerens, Matthias Freiberger, Marian Verhelst, Joni Dambre:
Hardware-aware mobile building block evaluation for computer vision. CoRR abs/2208.12694 (2022) - [i19]Nimish Shah, Wannes Meert, Marian Verhelst:
DPU-v2: Energy-efficient execution of irregular directed acyclic graphs. CoRR abs/2210.13184 (2022) - [i18]Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Frank K. Zenke, Frank K. Gürkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, S. Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu, Henk Corporaal:
CONVOLVE: Smart and seamless design of smart edge processors. CoRR abs/2212.00873 (2022) - [i17]Linyan Mei, Koen Goetschalckx, Arne Symons, Marian Verhelst:
DeFiNES: Enabling Fast Exploration of the Depth-first Scheduling Space for DNN Accelerators through Analytical Modeling. CoRR abs/2212.05344 (2022) - [i16]Arne Symons, Linyan Mei, Steven Colleman, Pouya Houshmand, Sebastian Karl, Marian Verhelst:
Towards Heterogeneous Multi-core Accelerators Exploiting Fine-grained Scheduling of Layer-Fused Deep Neural Networks. CoRR abs/2212.10612 (2022) - 2021
- [j52]Tom Vermeulen, Brecht Reynders, Fernando E. Rosas, Marian Verhelst, Sofie Pollin:
Performance analysis of in-band collision detection for dense wireless networks. EURASIP J. Wirel. Commun. Netw. 2021(1): 87 (2021) - [j51]Man Shi, Pouya Houshmand, Linyan Mei, Marian Verhelst:
Hardware-Efficient Residual Neural Network Execution in Line-Buffer Depth-First Processing. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(4): 690-700 (2021) - [j50]Linyan Mei, Pouya Houshmand, Vikram Jain, Juan Sebastian Piedrahita Giraldo, Marian Verhelst:
ZigZag: Enlarging Joint Architecture-Mapping Design Space Exploration for DNN Accelerators. IEEE Trans. Computers 70(8): 1160-1174 (2021) - [j49]Tom R. Molderez, Korneel Rabaey, Marian Verhelst:
A Scalable 128-Channel, Time-Multiplexed Potentiostat for Parallel Electrochemical Experiments. IEEE Trans. Circuits Syst. I Regul. Pap. 68(3): 1068-1079 (2021) - [j48]Juan Sebastian Piedrahita Giraldo, Marian Verhelst:
Hardware Acceleration for Embedded Keyword Spotting: Tutorial and Survey. ACM Trans. Embed. Comput. Syst. 20(6): 111:1-111:25 (2021) - [j47]Steven Colleman, Marian Verhelst:
High-Utilization, High-Flexibility Depth-First CNN Coprocessor for Image Pixel Processing on FPGA. IEEE Trans. Very Large Scale Integr. Syst. 29(3): 461-471 (2021) - [j46]Juan Sebastian Piedrahita Giraldo, Vikram Jain, Marian Verhelst:
Efficient Execution of Temporal Convolutional Networks for Embedded Keyword Spotting. IEEE Trans. Very Large Scale Integr. Syst. 29(12): 2220-2228 (2021) - [c105]Vikram Jain, Linyan Mei, Marian Verhelst:
Analyzing the Energy-Latency-Area-Accuracy Trade-off Across Contemporary Neural Networks. AICAS 2021: 1-4 - [c104]Arne Symons, Linyan Mei, Marian Verhelst:
LOMA: Fast Auto-Scheduling on DNN Accelerators through Loop-Order-based Memory Allocation. AICAS 2021: 1-4 - [c103]Peishuo Li, Tom R. Molderez, Marian Verhelst:
A 96-channel 40nm CMOS Fully-Integrated Potentiostat for Electrochemical Monitoring. ESSCIRC 2021: 167-170 - [c102]Peishuo Li, Tom R. Molderez, Marian Verhelst:
A 96-channel 40nm CMOS Fully-Integrated Potentiostat for Electrochemical Monitoring. ESSDERC 2021: 167-170 - [c101]Zuzana Jelcicová, Rasmus Jones, David Thorn Blix, Marian Verhelst, Jens Sparsø:
PeakRNN and StatsRNN: Dynamic Pruning in Recurrent Neural Networks. EUSIPCO 2021: 416-420 - [c100]Nimish Shah, Laura Isabel Galindez Olascoaga, Shirui Zhao, Wannes Meert, Marian Verhelst:
9.4 PIU: A 248GOPS/W Stream-Based Processor for Irregular Probabilistic Inference Networks Using Precision-Scalable Posit Arithmetic in 28nm. ISSCC 2021: 150-152 - [c99]Steven Colleman, Thomas Verelst, Linyan Mei, Tinne Tuytelaars, Marian Verhelst:
Processor Architecture Optimization for Spatially Dynamic Neural Networks. VLSI-SoC 2021: 1-6 - [c98]Koen Goetschalckx, Marian Verhelst:
DepFiN: A 12nm, 3.8TOPs depth-first CNN processor for high res. image processing. VLSI Circuits 2021: 1-2 - [i15]Nimish Shah, Laura Isabel Galindez Olascoaga, Wannes Meert, Marian Verhelst:
ProbLP: A framework for low-precision probabilistic inference. CoRR abs/2103.00216 (2021) - [i14]Nimish Shah, Laura Isabel Galindez Olascoaga, Wannes Meert, Marian Verhelst:
Acceleration of probabilistic reasoning through custom processor architecture. CoRR abs/2103.00266 (2021) - [i13]Nimish Shah, Wannes Meert, Marian Verhelst:
GRAPHOPT: constrained optimization-based parallelization of irregular graphs. CoRR abs/2105.01976 (2021) - [i12]Ehab M. Ibrahim, Linyan Mei, Marian Verhelst:
Survey and Benchmarking of Precision-Scalable MAC Arrays for Embedded DNN Processing. CoRR abs/2108.04773 (2021) - [i11]Nimish Shah, Laura Isabel Galindez Olascoaga, Shirui Zhao, Wannes Meert, Marian Verhelst:
DPU: DAG Processing Unit for Irregular Graphs with Precision-Scalable Posit Arithmetic in 28nm. CoRR abs/2112.05660 (2021) - 2020
- [j45]Juan Sebastian Piedrahita Giraldo, Steven Lauwereins, Komail M. H. Badami, Marian Verhelst:
Vocell: A 65-nm Speech-Triggered Wake-Up SoC for 10- $\mu$ W Keyword Spotting and Speaker Verification. IEEE J. Solid State Circuits 55(4): 868-878 (2020) - [j44]Athanasios T. Ramkaj, Juan Carlos Pena Ramos, Marcel J. M. Pelgrom, Michiel S. J. Steyaert, Marian Verhelst, Filip Tavernier:
A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS. IEEE J. Solid State Circuits 55(6): 1553-1564 (2020) - [j43]Fernando de la Hucha Arce, Marc Moonen, Marian Verhelst, Alexander Bertrand:
Distributed adaptive node-specific signal estimation in a wireless sensor network with noisy links. Signal Process. 166 (2020) - [j42]Fernando de la Hucha Arce, Panagiotis Patrinos, Marian Verhelst, Alexander Bertrand:
On the Convexity of Bit Depth Allocation for Linear MMSE Estimation in Wireless Sensor Networks. IEEE Signal Process. Lett. 27: 291-295 (2020) - [j41]Leandro Mateus Giacomini Rocha, Dwaipayan Biswas, Bram-Ernst Verhoef, Sergio Bampi, Chris Van Hoof, Mario Konijnenburg, Marian Verhelst, Nick Van Helleputte:
Binary CorNET: Accelerator for HR Estimation From Wrist-PPG. IEEE Trans. Biomed. Circuits Syst. 14(4): 715-726 (2020) - [c97]Nimish Shah, Laura Isabel Galindez Olascoaga, Wannes Meert, Marian Verhelst:
Acceleration of probabilistic reasoning through custom processor architecture. DATE 2020: 322-325 - [c96]Robby Neven, Marian Verhelst, Tinne Tuytelaars, Toon Goedemé:
Feed-Forward On-Edge Fine-Tuning Using Static Synthetic Gradient Modules. ECCV Workshops (5) 2020: 131-146 - [c95]Tom R. Molderez, Korneel Rabaey, Marian Verhelst:
An Affordable Multichannel Potentiostat with 128 Individual Stimulation and Sensing Channels. I2MTC 2020: 1-6 - [c94]Laura Isabel Galindez Olascoaga, Wannes Meert, Nimish Shah, Guy Van den Broeck, Marian Verhelst:
Discriminative Bias for Learning Probabilistic Sentential Decision Diagrams. IDA 2020: 184-196 - [c93]Laura Isabel Galindez Olascoaga, Wannes Meert, Nimish Shah, Marian Verhelst:
Dynamic Complexity Tuning for Hardware-Aware Probabilistic Circuits. IoT Streams/ITEM@PKDD/ECML 2020: 283-295 - [i10]Colby R. Banbury, Vijay Janapa Reddi, Max Lam, William Fu, Amin Fazel, Jeremy Holleman, Xinyuan Huang, Robert Hurtado, David Kanter, Anton Lokhmotov, David A. Patterson, Danilo Pau, Jae-sun Seo, Jeff Sieracki, Urmish Thakker, Marian Verhelst, Poonam Yadav:
Benchmarking TinyML Systems: Challenges and Direction. CoRR abs/2003.04821 (2020) - [i9]Linyan Mei, Pouya Houshmand, Vikram Jain, Juan Sebastian Piedrahita Giraldo, Marian Verhelst:
ZigZag: A Memory-Centric Rapid DNN Accelerator Design Space Exploration Framework. CoRR abs/2007.11360 (2020) - [i8]Robby Neven, Marian Verhelst, Tinne Tuytelaars, Toon Goedemé:
Feed-Forward On-Edge Fine-tuning Using Static Synthetic Gradient Modules. CoRR abs/2009.09675 (2020)
2010 – 2019
- 2019
- [j40]Koen Goetschalckx, Marian Verhelst:
Breaking High-Resolution CNN Bandwidth Barriers With Enhanced Depth-First Execution. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(2): 323-331 (2019) - [j39]Vincent Camus, Linyan Mei, Christian C. Enz, Marian Verhelst:
Review and Benchmarking of Precision-Scalable Multiply-Accumulate Unit Architectures for Embedded Neural-Network Processing. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(4): 697-711 (2019) - [j38]Daniel Bankman, Lita Yang, Bert Moons, Marian Verhelst, Boris Murmann:
An Always-On 3.8 $\mu$ J/86% CIFAR-10 Mixed-Signal Binary CNN Processor With All Memory on Chip in 28-nm CMOS. IEEE J. Solid State Circuits 54(1): 158-172 (2019) - [j37]Thomas Bos, Wentao Jiang, Jan D'hooge, Marian Verhelst, Wim Dehaene:
Enabling Ultrasound In-Body Communication: FIR Channel Models and QAM Experiments. IEEE Trans. Biomed. Circuits Syst. 13(1): 135-144 (2019) - [j36]Tom R. Molderez, Xu Zhang, Korneel Rabaey, Marian Verhelst:
A Current-Driven Six-Channel Potentiostat for Rapid Performance Characterization of Microbial Electrolysis Cells. IEEE Trans. Instrum. Meas. 68(12): 4694-4702 (2019) - [j35]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber:
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [c92]